[llvm-commits] [PATCH 2/4] (REVIEW REQUEST) Mips specific inline asm constraint 'I'
Jack Carter
jcarter at mips.com
Fri Apr 6 16:03:52 PDT 2012
A signed 16 bit constant.
The real test for this will be in the negative test.
#include <stdio.h>
main()
{
// Good: value is within range and is a short.
short s_input = 7;short s_result = 0;short s_val = 3;
__asm__ __volatile__(
"addi %0,%1,%2" : "=r" (s_result) : "r" (s_input), "I" (s_val));
printf ("mips_addi(%d,%d) = %d\n", s_input, s_val, s_result);
// Good per GCC: value is within range but is an int.
int i_val = 3;
__asm__ __volatile__(
"addi %0,%1,%2" : "=r" (s_result) : "r" (s_input), "I" (i_val));
printf ("mips_addi(%d,%d) = %d\n", s_input, i_val, i_result);
// Bad: value is outside of range even though marked as a short.
s_val = 0x00100000;
__asm__ __volatile__(
"addi %0,%1,%2" : "=r" (s_result) : "r" (s_input), "I" (s_val));
printf ("mips_addi(%d,%d) = %d\n", s_input, s_val, s_result);
}
---
lib/Target/Mips/MipsISelLowering.cpp | 46 ++++++++++++++++++++++++
lib/Target/Mips/MipsISelLowering.h | 9 +++++
test/CodeGen/Mips/inlineasm-cnstrnt-bad-I-1.ll | 19 ++++++++++
test/CodeGen/Mips/inlineasm_constraint.ll | 21 +++++++++++
4 files changed, 95 insertions(+), 0 deletions(-)
create mode 100644 test/CodeGen/Mips/inlineasm-cnstrnt-bad-I-1.ll
create mode 100644 test/CodeGen/Mips/inlineasm_constraint.ll
-------------- next part --------------
diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp
index 7af6b16..466a52a 100644
--- a/lib/Target/Mips/MipsISelLowering.cpp
+++ b/lib/Target/Mips/MipsISelLowering.cpp
@@ -2926,6 +2926,10 @@ MipsTargetLowering::getSingleConstraintMatchWeight(
if (type->isFloatTy())
weight = CW_Register;
break;
+ case 'I': // signed 16 bit immediate
+ if (isa<ConstantInt>(CallOperandVal))
+ weight = CW_Constant;
+ break;
}
return weight;
}
@@ -2959,6 +2963,48 @@ getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const
return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
}
+/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
+/// vector. If it is invalid, don't add anything to Ops.
+void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
+ std::string &Constraint,
+ std::vector<SDValue>&Ops,
+ SelectionDAG &DAG) const {
+ SDValue Result(0, 0);
+
+ // Only support length 1 constraints for now.
+ if (Constraint.length() > 1) return;
+
+ char ConstraintLetter = Constraint[0];
+ switch (ConstraintLetter) {
+ default: break; // This will fall through to the generic implementation
+ case 'I':
+ // If this fails, the parent routine will give an error
+ if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
+ if (!((Op.getValueType() == MVT::i16) || (Op.getValueType() == MVT::i32)))
+ return; // This will produce an error
+
+ // GCC allows both shorts and ints even though the spec states
+ // "signed 16 bit.
+ int32_t Val = (int)C->getZExtValue();
+ if (Op.getValueType() == MVT::i16) {
+ int16_t Sval = (int16_t)C->getZExtValue();
+ Val = (int32_t)Sval;
+ }
+ if ((Val < 32767) && (Val > -32767)) {
+ Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
+ break;
+ }
+ }
+ return;
+ }
+
+ if (Result.getNode()) {
+ Ops.push_back(Result);
+ return;
+ }
+ return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
+}
+
bool
MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
// The Mips target isn't yet aware of offsets.
diff --git a/lib/Target/Mips/MipsISelLowering.h b/lib/Target/Mips/MipsISelLowering.h
index 66f45cd..683f7fc 100644
--- a/lib/Target/Mips/MipsISelLowering.h
+++ b/lib/Target/Mips/MipsISelLowering.h
@@ -175,6 +175,15 @@ namespace llvm {
getRegForInlineAsmConstraint(const std::string &Constraint,
EVT VT) const;
+ /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
+ /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
+ /// true it means one of the asm constraint of the inline asm instruction
+ /// being processed is 'm'.
+ virtual void LowerAsmOperandForConstraint(SDValue Op,
+ std::string &Constraint,
+ std::vector<SDValue> &Ops,
+ SelectionDAG &DAG) const;
+
virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
/// isFPImmLegal - Returns true if the target can instruction select the
diff --git a/test/CodeGen/Mips/inlineasm-cnstrnt-bad-I-1.ll b/test/CodeGen/Mips/inlineasm-cnstrnt-bad-I-1.ll
new file mode 100644
index 0000000..fc5fdf2
--- /dev/null
+++ b/test/CodeGen/Mips/inlineasm-cnstrnt-bad-I-1.ll
@@ -0,0 +1,19 @@
+;XFAIL:
+;
+;This is a negative test. The constant value given for the constraint
+;is greater than 16 bits.
+;
+; RUN: not llc -march=mipsel < %s
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32"
+target triple = "mipsel-unknown-linux"
+
+ at .str = private unnamed_addr constant [23 x i8] c"mips_addi(%d,%d) = %d\0A\00", align 1
+
+define i32 @main() nounwind {
+entry:
+ %0 = tail call i32 asm sideeffect "addi $0,$1,$2", "=r,r,I"(i32 7, i32 1048576) nounwind, !srcloc !0
+ ret i32 0
+}
+
+!0 = metadata !{i32 183}
diff --git a/test/CodeGen/Mips/inlineasm_constraint.ll b/test/CodeGen/Mips/inlineasm_constraint.ll
new file mode 100644
index 0000000..4e392a2
--- /dev/null
+++ b/test/CodeGen/Mips/inlineasm_constraint.ll
@@ -0,0 +1,21 @@
+; RUN: llc -march=mipsel < %s | FileCheck %s
+
+define i32 @main() nounwind {
+entry:
+
+; First I with short
+; CHECK: #APP
+; CHECK: addi $3,$2,4096
+; CHECK: #NO_APP
+ %0 = tail call i16 asm sideeffect "addi $0,$1,$2", "=r,r,I"(i16 7, i16 4096) nounwind, !srcloc !0
+
+; Then I with int
+; CHECK: #APP
+; CHECK: addi $2,$2,-3
+; CHECK: #NO_APP
+ %1 = tail call i32 asm sideeffect "addi $0,$1,$2", "=r,r,I"(i32 7, i32 -3) nounwind, !srcloc !1
+ ret i32 0
+}
+
+!0 = metadata !{i32 133, i32 149}
+!1 = metadata !{i32 466}
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