[llvm-commits] [llvm] r146992 - /llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
Akira Hatanaka
ahatanaka at mips.com
Tue Dec 20 13:50:50 PST 2011
Author: ahatanak
Date: Tue Dec 20 15:50:49 2011
New Revision: 146992
URL: http://llvm.org/viewvc/llvm-project?rev=146992&view=rev
Log:
Add a pattern for matching zero-store with 64-bit address. The pattern is enabled
only when the target ABI is N64.
Modified:
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=146992&r1=146991&r2=146992&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Tue Dec 20 15:50:49 2011
@@ -1015,7 +1015,10 @@
def : Pat<(extloadi16_u addr:$src), (ULHu addr:$src)>;
// peepholes
-def : Pat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
+def : Pat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>,
+ Requires<[NotN64]>;
+def : Pat<(store (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>,
+ Requires<[IsN64]>;
// brcond patterns
multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
More information about the llvm-commits
mailing list