[llvm-commits] [llvm] r146990 - in /llvm/trunk: lib/Target/ARM/ARMInstrNEON.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/neon-vst-encoding.s
Jim Grosbach
grosbach at apple.com
Tue Dec 20 12:46:29 PST 2011
Author: grosbach
Date: Tue Dec 20 14:46:29 2011
New Revision: 146990
URL: http://llvm.org/viewvc/llvm-project?rev=146990&view=rev
Log:
ARM assembly parsing and encoding for VST2 single-element, double spaced.
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
llvm/trunk/test/MC/ARM/neon-vst-encoding.s
Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=146990&r1=146989&r2=146990&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Dec 20 14:46:29 2011
@@ -5800,6 +5800,10 @@
(ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
defm VST2LNdAsm : NEONDT32AsmPseudoInst<"vst2${p}", "$list, $addr",
(ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
+defm VST2LNqAsm : NEONDT16AsmPseudoInst<"vst2${p}", "$list, $addr",
+ (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
+defm VST2LNqAsm : NEONDT32AsmPseudoInst<"vst2${p}", "$list, $addr",
+ (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
defm VST2LNdWB_fixed_Asm : NEONDT8AsmPseudoInst<"vst2${p}", "$list, $addr!",
(ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
@@ -5807,6 +5811,10 @@
(ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
defm VST2LNdWB_fixed_Asm : NEONDT32AsmPseudoInst<"vst2${p}", "$list, $addr!",
(ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
+defm VST2LNqWB_fixed_Asm : NEONDT16AsmPseudoInst<"vst2${p}", "$list, $addr!",
+ (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
+defm VST2LNqWB_fixed_Asm : NEONDT32AsmPseudoInst<"vst2${p}", "$list, $addr!",
+ (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
defm VST2LNdWB_register_Asm :
NEONDT8AsmPseudoInst<"vst2${p}", "$list, $addr, $Rm",
(ins VecListTwoDByteIndexed:$list, addrmode6:$addr,
@@ -5819,6 +5827,14 @@
NEONDT32AsmPseudoInst<"vst2${p}", "$list, $addr, $Rm",
(ins VecListTwoDWordIndexed:$list, addrmode6:$addr,
rGPR:$Rm, pred:$p)>;
+defm VST2LNqWB_register_Asm :
+ NEONDT16AsmPseudoInst<"vst2${p}", "$list, $addr, $Rm",
+ (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr,
+ rGPR:$Rm, pred:$p)>;
+defm VST2LNqWB_register_Asm :
+ NEONDT32AsmPseudoInst<"vst2${p}", "$list, $addr, $Rm",
+ (ins VecListTwoQWordIndexed:$list, addrmode6:$addr,
+ rGPR:$Rm, pred:$p)>;
// VMOV takes an optional datatype suffix
defm : VFPDTAnyInstAlias<"vmov${p}", "$Vd, $Vm",
Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=146990&r1=146989&r2=146990&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Dec 20 14:46:29 2011
@@ -5118,84 +5118,134 @@
return false;
}
-static unsigned getRealVSTLNOpcode(unsigned Opc) {
+static unsigned getRealVSTLNOpcode(unsigned Opc, unsigned &Spacing) {
switch(Opc) {
default: assert(0 && "unexpected opcode!");
// VST1LN
case ARM::VST1LNdWB_fixed_Asm_8: case ARM::VST1LNdWB_fixed_Asm_P8:
case ARM::VST1LNdWB_fixed_Asm_I8: case ARM::VST1LNdWB_fixed_Asm_S8:
case ARM::VST1LNdWB_fixed_Asm_U8:
+ Spacing = 1;
return ARM::VST1LNd8_UPD;
case ARM::VST1LNdWB_fixed_Asm_16: case ARM::VST1LNdWB_fixed_Asm_P16:
case ARM::VST1LNdWB_fixed_Asm_I16: case ARM::VST1LNdWB_fixed_Asm_S16:
case ARM::VST1LNdWB_fixed_Asm_U16:
+ Spacing = 1;
return ARM::VST1LNd16_UPD;
case ARM::VST1LNdWB_fixed_Asm_32: case ARM::VST1LNdWB_fixed_Asm_F:
case ARM::VST1LNdWB_fixed_Asm_F32: case ARM::VST1LNdWB_fixed_Asm_I32:
case ARM::VST1LNdWB_fixed_Asm_S32: case ARM::VST1LNdWB_fixed_Asm_U32:
+ Spacing = 1;
return ARM::VST1LNd32_UPD;
case ARM::VST1LNdWB_register_Asm_8: case ARM::VST1LNdWB_register_Asm_P8:
case ARM::VST1LNdWB_register_Asm_I8: case ARM::VST1LNdWB_register_Asm_S8:
case ARM::VST1LNdWB_register_Asm_U8:
+ Spacing = 1;
return ARM::VST1LNd8_UPD;
case ARM::VST1LNdWB_register_Asm_16: case ARM::VST1LNdWB_register_Asm_P16:
case ARM::VST1LNdWB_register_Asm_I16: case ARM::VST1LNdWB_register_Asm_S16:
case ARM::VST1LNdWB_register_Asm_U16:
+ Spacing = 1;
return ARM::VST1LNd16_UPD;
case ARM::VST1LNdWB_register_Asm_32: case ARM::VST1LNdWB_register_Asm_F:
case ARM::VST1LNdWB_register_Asm_F32: case ARM::VST1LNdWB_register_Asm_I32:
case ARM::VST1LNdWB_register_Asm_S32: case ARM::VST1LNdWB_register_Asm_U32:
+ Spacing = 1;
return ARM::VST1LNd32_UPD;
case ARM::VST1LNdAsm_8: case ARM::VST1LNdAsm_P8:
case ARM::VST1LNdAsm_I8: case ARM::VST1LNdAsm_S8:
case ARM::VST1LNdAsm_U8:
+ Spacing = 1;
return ARM::VST1LNd8;
case ARM::VST1LNdAsm_16: case ARM::VST1LNdAsm_P16:
case ARM::VST1LNdAsm_I16: case ARM::VST1LNdAsm_S16:
case ARM::VST1LNdAsm_U16:
+ Spacing = 1;
return ARM::VST1LNd16;
case ARM::VST1LNdAsm_32: case ARM::VST1LNdAsm_F:
case ARM::VST1LNdAsm_F32: case ARM::VST1LNdAsm_I32:
case ARM::VST1LNdAsm_S32: case ARM::VST1LNdAsm_U32:
+ Spacing = 1;
return ARM::VST1LNd32;
// VST2LN
case ARM::VST2LNdWB_fixed_Asm_8: case ARM::VST2LNdWB_fixed_Asm_P8:
case ARM::VST2LNdWB_fixed_Asm_I8: case ARM::VST2LNdWB_fixed_Asm_S8:
case ARM::VST2LNdWB_fixed_Asm_U8:
+ Spacing = 1;
return ARM::VST2LNd8_UPD;
case ARM::VST2LNdWB_fixed_Asm_16: case ARM::VST2LNdWB_fixed_Asm_P16:
case ARM::VST2LNdWB_fixed_Asm_I16: case ARM::VST2LNdWB_fixed_Asm_S16:
case ARM::VST2LNdWB_fixed_Asm_U16:
+ Spacing = 1;
return ARM::VST2LNd16_UPD;
case ARM::VST2LNdWB_fixed_Asm_32: case ARM::VST2LNdWB_fixed_Asm_F:
case ARM::VST2LNdWB_fixed_Asm_F32: case ARM::VST2LNdWB_fixed_Asm_I32:
case ARM::VST2LNdWB_fixed_Asm_S32: case ARM::VST2LNdWB_fixed_Asm_U32:
+ Spacing = 1;
return ARM::VST2LNd32_UPD;
+ case ARM::VST2LNqWB_fixed_Asm_16: case ARM::VST2LNqWB_fixed_Asm_P16:
+ case ARM::VST2LNqWB_fixed_Asm_I16: case ARM::VST2LNqWB_fixed_Asm_S16:
+ case ARM::VST2LNqWB_fixed_Asm_U16:
+ Spacing = 2;
+ return ARM::VST2LNq16_UPD;
+ case ARM::VST2LNqWB_fixed_Asm_32: case ARM::VST2LNqWB_fixed_Asm_F:
+ case ARM::VST2LNqWB_fixed_Asm_F32: case ARM::VST2LNqWB_fixed_Asm_I32:
+ case ARM::VST2LNqWB_fixed_Asm_S32: case ARM::VST2LNqWB_fixed_Asm_U32:
+ Spacing = 2;
+ return ARM::VST2LNq32_UPD;
+
case ARM::VST2LNdWB_register_Asm_8: case ARM::VST2LNdWB_register_Asm_P8:
case ARM::VST2LNdWB_register_Asm_I8: case ARM::VST2LNdWB_register_Asm_S8:
case ARM::VST2LNdWB_register_Asm_U8:
+ Spacing = 1;
return ARM::VST2LNd8_UPD;
case ARM::VST2LNdWB_register_Asm_16: case ARM::VST2LNdWB_register_Asm_P16:
case ARM::VST2LNdWB_register_Asm_I16: case ARM::VST2LNdWB_register_Asm_S16:
case ARM::VST2LNdWB_register_Asm_U16:
+ Spacing = 1;
return ARM::VST2LNd16_UPD;
case ARM::VST2LNdWB_register_Asm_32: case ARM::VST2LNdWB_register_Asm_F:
case ARM::VST2LNdWB_register_Asm_F32: case ARM::VST2LNdWB_register_Asm_I32:
case ARM::VST2LNdWB_register_Asm_S32: case ARM::VST2LNdWB_register_Asm_U32:
+ Spacing = 1;
return ARM::VST2LNd32_UPD;
+ case ARM::VST2LNqWB_register_Asm_16: case ARM::VST2LNqWB_register_Asm_P16:
+ case ARM::VST2LNqWB_register_Asm_I16: case ARM::VST2LNqWB_register_Asm_S16:
+ case ARM::VST2LNqWB_register_Asm_U16:
+ Spacing = 2;
+ return ARM::VST2LNq16_UPD;
+ case ARM::VST2LNqWB_register_Asm_32: case ARM::VST2LNqWB_register_Asm_F:
+ case ARM::VST2LNqWB_register_Asm_F32: case ARM::VST2LNqWB_register_Asm_I32:
+ case ARM::VST2LNqWB_register_Asm_S32: case ARM::VST2LNqWB_register_Asm_U32:
+ Spacing = 2;
+ return ARM::VST2LNq32_UPD;
+
case ARM::VST2LNdAsm_8: case ARM::VST2LNdAsm_P8:
case ARM::VST2LNdAsm_I8: case ARM::VST2LNdAsm_S8:
case ARM::VST2LNdAsm_U8:
+ Spacing = 1;
return ARM::VST2LNd8;
case ARM::VST2LNdAsm_16: case ARM::VST2LNdAsm_P16:
case ARM::VST2LNdAsm_I16: case ARM::VST2LNdAsm_S16:
case ARM::VST2LNdAsm_U16:
+ Spacing = 1;
return ARM::VST2LNd16;
case ARM::VST2LNdAsm_32: case ARM::VST2LNdAsm_F:
case ARM::VST2LNdAsm_F32: case ARM::VST2LNdAsm_I32:
case ARM::VST2LNdAsm_S32: case ARM::VST2LNdAsm_U32:
+ Spacing = 1;
return ARM::VST2LNd32;
+ case ARM::VST2LNqAsm_16: case ARM::VST2LNqAsm_P16:
+ case ARM::VST2LNqAsm_I16: case ARM::VST2LNqAsm_S16:
+ case ARM::VST2LNqAsm_U16:
+ Spacing = 2;
+ return ARM::VST2LNq16;
+ case ARM::VST2LNqAsm_32: case ARM::VST2LNqAsm_F:
+ case ARM::VST2LNqAsm_F32: case ARM::VST2LNqAsm_I32:
+ case ARM::VST2LNqAsm_S32: case ARM::VST2LNqAsm_U32:
+ Spacing = 2;
+ return ARM::VST2LNq32;
}
}
@@ -5344,7 +5394,8 @@
MCInst TmpInst;
// Shuffle the operands around so the lane index operand is in the
// right place.
- TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode()));
+ unsigned Spacing;
+ TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(2)); // Rn
TmpInst.addOperand(Inst.getOperand(3)); // alignment
@@ -5357,24 +5408,32 @@
return true;
}
- case ARM::VST2LNdWB_register_Asm_8: case ARM::VST2LNdWB_register_Asm_P8:
- case ARM::VST2LNdWB_register_Asm_I8: case ARM::VST2LNdWB_register_Asm_S8:
- case ARM::VST2LNdWB_register_Asm_U8: case ARM::VST2LNdWB_register_Asm_16:
+ case ARM::VST2LNdWB_register_Asm_8: case ARM::VST2LNdWB_register_Asm_P8:
+ case ARM::VST2LNdWB_register_Asm_I8: case ARM::VST2LNdWB_register_Asm_S8:
+ case ARM::VST2LNdWB_register_Asm_U8: case ARM::VST2LNdWB_register_Asm_16:
case ARM::VST2LNdWB_register_Asm_P16: case ARM::VST2LNdWB_register_Asm_I16:
case ARM::VST2LNdWB_register_Asm_S16: case ARM::VST2LNdWB_register_Asm_U16:
- case ARM::VST2LNdWB_register_Asm_32: case ARM::VST2LNdWB_register_Asm_F:
+ case ARM::VST2LNdWB_register_Asm_32: case ARM::VST2LNdWB_register_Asm_F:
case ARM::VST2LNdWB_register_Asm_F32: case ARM::VST2LNdWB_register_Asm_I32:
- case ARM::VST2LNdWB_register_Asm_S32: case ARM::VST2LNdWB_register_Asm_U32: {
+ case ARM::VST2LNdWB_register_Asm_S32: case ARM::VST2LNdWB_register_Asm_U32:
+ case ARM::VST2LNqWB_register_Asm_16: case ARM::VST2LNqWB_register_Asm_P16:
+ case ARM::VST2LNqWB_register_Asm_I16: case ARM::VST2LNqWB_register_Asm_S16:
+ case ARM::VST2LNqWB_register_Asm_U16: case ARM::VST2LNqWB_register_Asm_32:
+ case ARM::VST2LNqWB_register_Asm_F: case ARM::VST2LNqWB_register_Asm_F32:
+ case ARM::VST2LNqWB_register_Asm_I32: case ARM::VST2LNqWB_register_Asm_S32:
+ case ARM::VST2LNqWB_register_Asm_U32: {
MCInst TmpInst;
// Shuffle the operands around so the lane index operand is in the
// right place.
- TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode()));
+ unsigned Spacing;
+ TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(2)); // Rn
TmpInst.addOperand(Inst.getOperand(3)); // alignment
TmpInst.addOperand(Inst.getOperand(4)); // Rm
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg()+1));
+ TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ Spacing));
TmpInst.addOperand(Inst.getOperand(1)); // lane
TmpInst.addOperand(Inst.getOperand(5)); // CondCode
TmpInst.addOperand(Inst.getOperand(6));
@@ -5392,7 +5451,8 @@
MCInst TmpInst;
// Shuffle the operands around so the lane index operand is in the
// right place.
- TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode()));
+ unsigned Spacing;
+ TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(2)); // Rn
TmpInst.addOperand(Inst.getOperand(3)); // alignment
@@ -5405,24 +5465,32 @@
return true;
}
- case ARM::VST2LNdWB_fixed_Asm_8: case ARM::VST2LNdWB_fixed_Asm_P8:
- case ARM::VST2LNdWB_fixed_Asm_I8: case ARM::VST2LNdWB_fixed_Asm_S8:
- case ARM::VST2LNdWB_fixed_Asm_U8: case ARM::VST2LNdWB_fixed_Asm_16:
+ case ARM::VST2LNdWB_fixed_Asm_8: case ARM::VST2LNdWB_fixed_Asm_P8:
+ case ARM::VST2LNdWB_fixed_Asm_I8: case ARM::VST2LNdWB_fixed_Asm_S8:
+ case ARM::VST2LNdWB_fixed_Asm_U8: case ARM::VST2LNdWB_fixed_Asm_16:
case ARM::VST2LNdWB_fixed_Asm_P16: case ARM::VST2LNdWB_fixed_Asm_I16:
case ARM::VST2LNdWB_fixed_Asm_S16: case ARM::VST2LNdWB_fixed_Asm_U16:
- case ARM::VST2LNdWB_fixed_Asm_32: case ARM::VST2LNdWB_fixed_Asm_F:
+ case ARM::VST2LNdWB_fixed_Asm_32: case ARM::VST2LNdWB_fixed_Asm_F:
case ARM::VST2LNdWB_fixed_Asm_F32: case ARM::VST2LNdWB_fixed_Asm_I32:
- case ARM::VST2LNdWB_fixed_Asm_S32: case ARM::VST2LNdWB_fixed_Asm_U32: {
+ case ARM::VST2LNdWB_fixed_Asm_S32: case ARM::VST2LNdWB_fixed_Asm_U32:
+ case ARM::VST2LNqWB_fixed_Asm_16: case ARM::VST2LNqWB_fixed_Asm_P16:
+ case ARM::VST2LNqWB_fixed_Asm_I16: case ARM::VST2LNqWB_fixed_Asm_S16:
+ case ARM::VST2LNqWB_fixed_Asm_U16: case ARM::VST2LNqWB_fixed_Asm_32:
+ case ARM::VST2LNqWB_fixed_Asm_F: case ARM::VST2LNqWB_fixed_Asm_F32:
+ case ARM::VST2LNqWB_fixed_Asm_I32: case ARM::VST2LNqWB_fixed_Asm_S32:
+ case ARM::VST2LNqWB_fixed_Asm_U32: {
MCInst TmpInst;
// Shuffle the operands around so the lane index operand is in the
// right place.
- TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode()));
+ unsigned Spacing;
+ TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(2)); // Rn
TmpInst.addOperand(Inst.getOperand(3)); // alignment
TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg()+1));
+ TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ Spacing));
TmpInst.addOperand(Inst.getOperand(1)); // lane
TmpInst.addOperand(Inst.getOperand(4)); // CondCode
TmpInst.addOperand(Inst.getOperand(5));
@@ -5438,7 +5506,8 @@
MCInst TmpInst;
// Shuffle the operands around so the lane index operand is in the
// right place.
- TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode()));
+ unsigned Spacing;
+ TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(2)); // Rn
TmpInst.addOperand(Inst.getOperand(3)); // alignment
TmpInst.addOperand(Inst.getOperand(0)); // Vd
@@ -5449,20 +5518,25 @@
return true;
}
- case ARM::VST2LNdAsm_8: case ARM::VST2LNdAsm_P8: case ARM::VST2LNdAsm_I8:
- case ARM::VST2LNdAsm_S8: case ARM::VST2LNdAsm_U8: case ARM::VST2LNdAsm_16:
+ case ARM::VST2LNdAsm_8: case ARM::VST2LNdAsm_P8: case ARM::VST2LNdAsm_I8:
+ case ARM::VST2LNdAsm_S8: case ARM::VST2LNdAsm_U8: case ARM::VST2LNdAsm_16:
case ARM::VST2LNdAsm_P16: case ARM::VST2LNdAsm_I16: case ARM::VST2LNdAsm_S16:
- case ARM::VST2LNdAsm_U16: case ARM::VST2LNdAsm_32: case ARM::VST2LNdAsm_F:
+ case ARM::VST2LNdAsm_U16: case ARM::VST2LNdAsm_32: case ARM::VST2LNdAsm_F:
case ARM::VST2LNdAsm_F32: case ARM::VST2LNdAsm_I32: case ARM::VST2LNdAsm_S32:
- case ARM::VST2LNdAsm_U32: {
+ case ARM::VST2LNdAsm_U32: case ARM::VST2LNqAsm_16: case ARM::VST2LNqAsm_P16:
+ case ARM::VST2LNqAsm_I16: case ARM::VST2LNqAsm_S16: case ARM::VST2LNqAsm_U16:
+ case ARM::VST2LNqAsm_32: case ARM::VST2LNqAsm_F: case ARM::VST2LNqAsm_F32:
+ case ARM::VST2LNqAsm_I32: case ARM::VST2LNqAsm_S32: case ARM::VST2LNqAsm_U32:{
MCInst TmpInst;
// Shuffle the operands around so the lane index operand is in the
// right place.
- TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode()));
+ unsigned Spacing;
+ TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode(), Spacing));
TmpInst.addOperand(Inst.getOperand(2)); // Rn
TmpInst.addOperand(Inst.getOperand(3)); // alignment
TmpInst.addOperand(Inst.getOperand(0)); // Vd
- TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg()+1));
+ TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
+ Spacing));
TmpInst.addOperand(Inst.getOperand(1)); // lane
TmpInst.addOperand(Inst.getOperand(4)); // CondCode
TmpInst.addOperand(Inst.getOperand(5));
@@ -5504,11 +5578,12 @@
case ARM::VLD2LNdWB_register_Asm_32: case ARM::VLD2LNdWB_register_Asm_F:
case ARM::VLD2LNdWB_register_Asm_F32: case ARM::VLD2LNdWB_register_Asm_I32:
case ARM::VLD2LNdWB_register_Asm_S32: case ARM::VLD2LNdWB_register_Asm_U32:
- case ARM::VLD2LNqWB_register_Asm_P16: case ARM::VLD2LNqWB_register_Asm_I16:
- case ARM::VLD2LNqWB_register_Asm_S16: case ARM::VLD2LNqWB_register_Asm_U16:
- case ARM::VLD2LNqWB_register_Asm_32: case ARM::VLD2LNqWB_register_Asm_F:
- case ARM::VLD2LNqWB_register_Asm_F32: case ARM::VLD2LNqWB_register_Asm_I32:
- case ARM::VLD2LNqWB_register_Asm_S32: case ARM::VLD2LNqWB_register_Asm_U32: {
+ case ARM::VLD2LNqWB_register_Asm_16: case ARM::VLD2LNqWB_register_Asm_P16:
+ case ARM::VLD2LNqWB_register_Asm_I16: case ARM::VLD2LNqWB_register_Asm_S16:
+ case ARM::VLD2LNqWB_register_Asm_U16: case ARM::VLD2LNqWB_register_Asm_32:
+ case ARM::VLD2LNqWB_register_Asm_F: case ARM::VLD2LNqWB_register_Asm_F32:
+ case ARM::VLD2LNqWB_register_Asm_I32: case ARM::VLD2LNqWB_register_Asm_S32:
+ case ARM::VLD2LNqWB_register_Asm_U32: {
MCInst TmpInst;
// Shuffle the operands around so the lane index operand is in the
// right place.
@@ -5565,11 +5640,12 @@
case ARM::VLD2LNdWB_fixed_Asm_32: case ARM::VLD2LNdWB_fixed_Asm_F:
case ARM::VLD2LNdWB_fixed_Asm_F32: case ARM::VLD2LNdWB_fixed_Asm_I32:
case ARM::VLD2LNdWB_fixed_Asm_S32: case ARM::VLD2LNdWB_fixed_Asm_U32:
- case ARM::VLD2LNqWB_fixed_Asm_P16: case ARM::VLD2LNqWB_fixed_Asm_I16:
- case ARM::VLD2LNqWB_fixed_Asm_S16: case ARM::VLD2LNqWB_fixed_Asm_U16:
- case ARM::VLD2LNqWB_fixed_Asm_32: case ARM::VLD2LNqWB_fixed_Asm_F:
- case ARM::VLD2LNqWB_fixed_Asm_F32: case ARM::VLD2LNqWB_fixed_Asm_I32:
- case ARM::VLD2LNqWB_fixed_Asm_S32: case ARM::VLD2LNqWB_fixed_Asm_U32: {
+ case ARM::VLD2LNqWB_fixed_Asm_16: case ARM::VLD2LNqWB_fixed_Asm_P16:
+ case ARM::VLD2LNqWB_fixed_Asm_I16: case ARM::VLD2LNqWB_fixed_Asm_S16:
+ case ARM::VLD2LNqWB_fixed_Asm_U16: case ARM::VLD2LNqWB_fixed_Asm_32:
+ case ARM::VLD2LNqWB_fixed_Asm_F: case ARM::VLD2LNqWB_fixed_Asm_F32:
+ case ARM::VLD2LNqWB_fixed_Asm_I32: case ARM::VLD2LNqWB_fixed_Asm_S32:
+ case ARM::VLD2LNqWB_fixed_Asm_U32: {
MCInst TmpInst;
// Shuffle the operands around so the lane index operand is in the
// right place.
@@ -5592,10 +5668,10 @@
return true;
}
- case ARM::VLD1LNdAsm_8: case ARM::VLD1LNdAsm_P8: case ARM::VLD1LNdAsm_I8:
- case ARM::VLD1LNdAsm_S8: case ARM::VLD1LNdAsm_U8: case ARM::VLD1LNdAsm_16:
+ case ARM::VLD1LNdAsm_8: case ARM::VLD1LNdAsm_P8: case ARM::VLD1LNdAsm_I8:
+ case ARM::VLD1LNdAsm_S8: case ARM::VLD1LNdAsm_U8: case ARM::VLD1LNdAsm_16:
case ARM::VLD1LNdAsm_P16: case ARM::VLD1LNdAsm_I16: case ARM::VLD1LNdAsm_S16:
- case ARM::VLD1LNdAsm_U16: case ARM::VLD1LNdAsm_32: case ARM::VLD1LNdAsm_F:
+ case ARM::VLD1LNdAsm_U16: case ARM::VLD1LNdAsm_32: case ARM::VLD1LNdAsm_F:
case ARM::VLD1LNdAsm_F32: case ARM::VLD1LNdAsm_I32: case ARM::VLD1LNdAsm_S32:
case ARM::VLD1LNdAsm_U32: {
MCInst TmpInst;
Modified: llvm/trunk/test/MC/ARM/neon-vst-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-vst-encoding.s?rev=146990&r1=146989&r2=146990&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-vst-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neon-vst-encoding.s Tue Dec 20 14:46:29 2011
@@ -101,23 +101,37 @@
vst2.8 {d16[1], d17[1]}, [r0, :16]
vst2.16 {d16[1], d17[1]}, [r0, :32]
vst2.32 {d16[1], d17[1]}, [r0]
-@ vst2.16 {d17[1], d19[1]}, [r0]
-@ vst2.32 {d17[0], d19[0]}, [r0, :64]
+ vst2.16 {d17[1], d19[1]}, [r0]
+ vst2.32 {d17[0], d19[0]}, [r0, :64]
vst2.8 {d2[4], d3[4]}, [r2], r3
vst2.8 {d2[4], d3[4]}, [r2]!
vst2.8 {d2[4], d3[4]}, [r2]
+ vst2.16 {d17[1], d19[1]}, [r0]
+ vst2.32 {d17[0], d19[0]}, [r0, :64]
+ vst2.16 {d7[1], d9[1]}, [r1]!
+ vst2.32 {d6[0], d8[0]}, [r2, :64]!
+ vst2.16 {d2[1], d4[1]}, [r3], r5
+ vst2.32 {d5[0], d7[0]}, [r4, :64], r7
+
@ CHECK: vst2.8 {d16[1], d17[1]}, [r0, :16] @ encoding: [0x3f,0x01,0xc0,0xf4]
@ CHECK: vst2.16 {d16[1], d17[1]}, [r0, :32] @ encoding: [0x5f,0x05,0xc0,0xf4]
@ CHECK: vst2.32 {d16[1], d17[1]}, [r0] @ encoding: [0x8f,0x09,0xc0,0xf4]
-@ FIXME: vst2.16 {d17[1], d19[1]}, [r0] @ encoding: [0x6f,0x15,0xc0,0xf4]
-@ FIXME: vst2.32 {d17[0], d19[0]}, [r0, :64] @ encoding: [0x5f,0x19,0xc0,0xf4]
+@ CHECK: vst2.16 {d17[1], d19[1]}, [r0] @ encoding: [0x6f,0x15,0xc0,0xf4]
+@ CHECK: vst2.32 {d17[0], d19[0]}, [r0, :64] @ encoding: [0x5f,0x19,0xc0,0xf4]
@ CHECK: vst2.8 {d2[4], d3[4]}, [r2], r3 @ encoding: [0x83,0x21,0x82,0xf4]
@ CHECK: vst2.8 {d2[4], d3[4]}, [r2]! @ encoding: [0x8d,0x21,0x82,0xf4]
@ CHECK: vst2.8 {d2[4], d3[4]}, [r2] @ encoding: [0x8f,0x21,0x82,0xf4]
+@ CHECK: vst2.16 {d17[1], d19[1]}, [r0] @ encoding: [0x6f,0x15,0xc0,0xf4]
+@ CHECK: vst2.32 {d17[0], d19[0]}, [r0, :64] @ encoding: [0x5f,0x19,0xc0,0xf4]
+@ CHECK: vst2.16 {d7[1], d9[1]}, [r1]! @ encoding: [0x6d,0x75,0x81,0xf4]
+@ CHECK: vst2.32 {d6[0], d8[0]}, [r2, :64]! @ encoding: [0x5d,0x69,0x82,0xf4]
+@ CHECK: vst2.16 {d2[1], d4[1]}, [r3], r5 @ encoding: [0x65,0x25,0x83,0xf4]
+@ CHECK: vst2.32 {d5[0], d7[0]}, [r4, :64], r7 @ encoding: [0x57,0x59,0x84,0xf4]
+
@ vst3.8 {d16[1], d17[1], d18[1]}, [r0]
@ vst3.16 {d16[1], d17[1], d18[1]}, [r0]
More information about the llvm-commits
mailing list