[llvm-commits] PATCH: Enable direct selection of bsf and bsr instructions for cttz and ctlz with zero-undef behavior

Chandler Carruth chandlerc at gmail.com
Sat Dec 17 02:29:35 PST 2011

On Thu, Dec 15, 2011 at 7:52 AM, Stephen Canon <scanon at apple.com> wrote:

> Just for the record, this is in no way unique to AMD.  Agner Fog's tables
> list BSF/BSR as 10 µops/16 cycles on Atom as well.  BSF is a hazard to be
> avoided on an unknown x86 processor.

I really wasn't trying to draw generalizations. I've read the same tables.
=/ I'm not sure what your concerned about here, this patch is orthogonal to
any work on avoiding these instructions on architectures where they just
decode to silly microcode.

I'd still really appreciate some review on the actual patch. It's pretty
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