[llvm-commits] [llvm] r146096 - in /llvm/trunk: lib/Target/Mips/Mips64InstrInfo.td test/CodeGen/Mips/mips64ext.ll

[Akira Hatanaka]

Author: ahatanak
Date: Wed Dec  7 17:14:41 2011
New Revision: 146096

URL: http://llvm.org/viewvc/llvm-project?rev=146096&view=rev
Log:
32 to 64-bit zext pattern.


Added:
    llvm/trunk/test/CodeGen/Mips/mips64ext.ll
Modified:
    llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td

Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=146096&r1=146095&r2=146096&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Wed Dec  7 17:14:41 2011
@@ -222,6 +222,9 @@
 def DEXT : ExtBase<3, "dext", CPU64Regs>;
 def DINS : InsBase<7, "dins", CPU64Regs>;
 
+def DSLL64_32 : FR<0x3c, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt),
+                   "dsll32\t$rd, $rt, 0", [], IIAlu>;
+
 //===----------------------------------------------------------------------===//
 //  Arbitrary patterns that map to one or more instructions
 //===----------------------------------------------------------------------===//
@@ -296,3 +299,5 @@
 def : Pat<(i32 (trunc CPU64Regs:$src)),
           (SLL (EXTRACT_SUBREG CPU64Regs:$src, sub_32), 0)>, Requires<[IsN64]>;
  
+// 32-to-64-bit extension
+def : Pat<(i64 (zext CPURegs:$src)), (DSRL32 (DSLL64_32 CPURegs:$src), 0)>;

Added: llvm/trunk/test/CodeGen/Mips/mips64ext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/mips64ext.ll?rev=146096&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/mips64ext.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/mips64ext.ll Wed Dec  7 17:14:41 2011
@@ -0,0 +1,11 @@
+; RUN: llc  < %s -march=mips64el -mcpu=mips64 -mattr=n64 | FileCheck %s 
+
+define i64 @zext64_32(i32 %a) nounwind readnone {
+entry:
+; CHECK: addiu $[[R0:[0-9]+]], ${{[0-9]+}}, 2
+; CHECK: dsll32 $[[R1:[0-9]+]], $[[R0]], 0
+; CHECK: dsrl32  ${{[0-9]+}}, $[[R1]], 0
+  %add = add i32 %a, 2
+  %conv = zext i32 %add to i64
+  ret i64 %conv
+}