[llvm-commits] AVX1 Code Generation - VSHUFP extension

[Demikhovsky, Elena]

Eli,

Thank you for the review.
I fixed the code. The input mask remains unchanged now.
Please take a look.

- Elena

-----Original Message-----
From: Eli Friedman [mailto:eli.friedman at gmail.com] 
Sent: Monday, November 07, 2011 23:47
To: Demikhovsky, Elena
Cc: llvm-commits at cs.uiuc.edu
Subject: Re: [llvm-commits] AVX1 Code Generation - VSHUFP extension

On Mon, Nov 7, 2011 at 12:08 AM, Demikhovsky, Elena
<elena.demikhovsky at intel.com> wrote:
> Hello,
>
> I added several lines in X86 code generator that allow to choose VSHUFPS/VSHUFPD
> instructions while lowering VECTOR_SHUFFLE node. I check a commuted VSHUFP mask.
>
> I extended the existing lit test.
>
> Please review.

+static bool isCommutedVSHUFPSY(SmallVectorImpl<int> &Mask, EVT VT,
+                               const X86Subtarget *Subtarget) {
+
+  if ((VT.getSizeInBits() != 256) || (VT.getVectorNumElements() != 8))
+    return false;
+
+  CommuteVectorShuffleMask(Mask, VT);
+  return isVSHUFPSYMask(Mask, VT, Subtarget);
+}

It looks like this mutates the input Mask; I don't think you really
want to do that.

+  // Try to swap operands in the node to match x86 shuffle ops
+  if (!V2IsUndef && isCommutedVSHUFPSY(M, VT, Subtarget)) {
+    // Now we need to commute operands.
+    SVOp = cast<ShuffleVectorSDNode>(CommuteVectorShuffle(SVOp, DAG));

This isn't consistent with the way other code in this function uses
CommuteVectorShuffle.

-Eli
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