[llvm-commits] DAGCombine optimization triggers a scheduler bug

[Rotem, Nadav]

Hi,

I added a degcombine optimization which triggers a scheduler bug and causes two tests to fail:

    LLVM :: CodeGen/X86/vec_zero_cse.ll
    LLVM :: CodeGen/X86/widen_cast-6.ll

With the assertions:

llc: /..../llvm-head/llvm/include/llvm/CodeGen/MachineOperand.h:227: unsigned int llvm::MachineOperand::getSubReg() const: Assertion
`isReg() && "Wrong MachineOperand accessor"' failed.

llc: /..../llvm/llvm-head/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp:264: unsigned int llvm::InstrEmitter::getVR(llvm::SDValue, llvm:
:DenseMap<llvm::SDValue, unsigned int, llvm::DenseMapInfo<llvm::SDValue>, llvm::DenseMapInfo<unsigned int> >&): Assertion `I != VRBaseMap.end() && "Node emitt
ed out of order - late"' failed.

These are tiny tests and this patch can be useful to anyone who attempts to debug the scheduler.

Cheers,
Nadav
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