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</o:shapelayout></xml><![endif]--></head><body lang=EN-US link=blue vlink=purple><div class=WordSection1><p class=MsoNormal>Hi, <o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>I added a degcombine optimization which triggers a scheduler bug and causes two tests to fail:<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal> LLVM :: CodeGen/X86/vec_zero_cse.ll<o:p></o:p></p><p class=MsoNormal> LLVM :: CodeGen/X86/widen_cast-6.ll<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>With the assertions:<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>llc: /…./llvm-head/llvm/include/llvm/CodeGen/MachineOperand.h:227: unsigned int llvm::MachineOperand::getSubReg() const: Assertion<o:p></o:p></p><p class=MsoNormal> `isReg() && "Wrong MachineOperand accessor"' failed.<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>llc: /…./llvm/llvm-head/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp:264: unsigned int llvm::InstrEmitter::getVR(llvm::SDValue, llvm:<o:p></o:p></p><p class=MsoNormal>:DenseMap<llvm::SDValue, unsigned int, llvm::DenseMapInfo<llvm::SDValue>, llvm::DenseMapInfo<unsigned int> >&): Assertion `I != VRBaseMap.end() && "Node emitt<o:p></o:p></p><p class=MsoNormal>ed out of order - late"' failed.<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>These are tiny tests and this patch can be useful to anyone who attempts to debug the scheduler. <o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>Cheers, <o:p></o:p></p><p class=MsoNormal>Nadav<o:p></o:p></p></div><font face="monospace">---------------------------------------------------------------------<br>
Intel Israel (74) Limited<br>
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