[llvm-commits] [llvm] r142440 - /llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

[Jim Grosbach]

On Oct 18, 2011, at 3:52 PM, Bill Wendling <isanbard at gmail.com> wrote:

> Author: void
> Date: Tue Oct 18 17:52:20 2011
> New Revision: 142440
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=142440&view=rev
> Log:
> Use the integer compare when the value is small enough. Use the "move into a
> register and then compare against that" method when it's too large. We have to
> move the value into the register in the "movw, movt" pair of instructions.
> 
> 
> Modified:
>    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=142440&r1=142439&r2=142440&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Oct 18 17:52:20 2011
> @@ -5672,9 +5672,7 @@
>   MachineRegisterInfo *MRI = &MF->getRegInfo();
>   ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>();
>   MachineFrameInfo *MFI = MF->getFrameInfo();
> -  MachineConstantPool *MCP = MF->getConstantPool();
>   int FI = MFI->getFunctionContextIndex();
> -  const Function *F = MF->getFunction();
> 
>   const TargetRegisterClass *TRC =
>     Subtarget->isThumb() ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
> @@ -5863,6 +5861,23 @@
>                    .addImm(4)
>                    .addMemOperand(FIMMOLd));
> 
> +    if (NumLPads < 256) {
> +      AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPri))
> +                     .addReg(NewVReg1)
> +                     .addImm(NumLPads));
> +    } else {
> +      unsigned VReg1 = MRI->createVirtualRegister(TRC);
> +      AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVi16), VReg1)
> +                     .addImm(NumLPads & 0xFF));

0xffff right?

> +      unsigned VReg2 = MRI->createVirtualRegister(TRC);
> +      AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVTi16), VReg2)
> +                     .addReg(VReg1)
> +                     .addImm(NumLPads >> 16));

We don't need the second instruction if it's between 256 and 64k(?)

> +      AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
> +                     .addReg(NewVReg1)
> +                     .addReg(VReg2));
> +    }
> +
>     unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
>     AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVi16), NewVReg2)
>                    .addImm(LPadList.size()));
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits