[llvm-commits] [llvm] r139830 - /llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s

[Jim Grosbach]

Author: grosbach
Date: Thu Sep 15 14:50:04 2011
New Revision: 139830

URL: http://llvm.org/viewvc/llvm-project?rev=139830&view=rev
Log:
Thumb2 assembly parsing and encoding for ROR.

Modified:
    llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s

Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=139830&r1=139829&r2=139830&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Thu Sep 15 14:50:04 2011
@@ -1474,6 +1474,44 @@
 
 
 @------------------------------------------------------------------------------
+@ ROR (immediate)
+ at ------------------------------------------------------------------------------
+        ror r2, r3, #12
+        rors r8, r3, #31
+        rors.w r2, r3, #1
+        ror r2, r3, #4
+        rors r2, r12, #15
+
+        ror r3, #19
+        rors r8, #2
+        rors.w r7, #5
+        ror.w r12, #21
+
+@ CHECK: ror.w	r2, r3, #12             @ encoding: [0x4f,0xea,0x33,0x32]
+@ CHECK: rors.w	r8, r3, #31             @ encoding: [0x5f,0xea,0xf3,0x78]
+@ CHECK: rors.w	r2, r3, #1              @ encoding: [0x5f,0xea,0x73,0x02]
+@ CHECK: ror.w	r2, r3, #4              @ encoding: [0x4f,0xea,0x33,0x12]
+@ CHECK: rors.w	r2, r12, #15            @ encoding: [0x5f,0xea,0xfc,0x32]
+
+@ CHECK: ror.w	r3, r3, #19             @ encoding: [0x4f,0xea,0xf3,0x43]
+@ CHECK: rors.w	r8, r8, #2              @ encoding: [0x5f,0xea,0xb8,0x08]
+@ CHECK: rors.w	r7, r7, #5              @ encoding: [0x5f,0xea,0x77,0x17]
+@ CHECK: ror.w	r12, r12, #21           @ encoding: [0x4f,0xea,0x7c,0x5c]
+
+
+ at ------------------------------------------------------------------------------
+@ ROR (register)
+ at ------------------------------------------------------------------------------
+        ror r3, r4, r2
+        ror.w r1, r2
+        rors r3, r4, r8
+
+@ CHECK: ror.w	r3, r4, r2              @ encoding: [0x64,0xfa,0x02,0xf3]
+@ CHECK: ror.w	r1, r1, r2              @ encoding: [0x61,0xfa,0x02,0xf1]
+@ CHECK: rors.w	r3, r4, r8              @ encoding: [0x74,0xfa,0x08,0xf3]
+
+
+ at ------------------------------------------------------------------------------
 @ SUB (register)
 @------------------------------------------------------------------------------
         sub.w r5, r2, r12, rrx