[llvm-commits] [llvm] r139528 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/avx-blend.ll test/CodeGen/X86/sse41-blend.ll
Bruno Cardoso Lopes
bruno.cardoso at gmail.com
Mon Sep 12 12:47:48 PDT 2011
This is actually wrong, will commit a fix soon
On Monday, September 12, 2011, Bruno Cardoso Lopes <bruno.cardoso at gmail.com>
wrote:
> Author: bruno
> Date: Mon Sep 12 14:30:40 2011
> New Revision: 139528
>
> URL: http://llvm.org/viewvc/llvm-project?rev=139528&view=rev
> Log:
> Not sure how CMPPS and CMPPD had already ever worked, I guess it didn't.
> However with this fix it does now.
>
> Basically the operand order for the x86 target specific node
> is not the same as the instruction, but since the intrinsic need that
> specific order at the instruction definition, just change the order
> during legalization. Also, there were some wrong invertions of condition
> codes, such as GE => LE, GT => LT, fix that too. Fix PR10907.
>
> Modified:
> llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> llvm/trunk/test/CodeGen/X86/avx-blend.ll
> llvm/trunk/test/CodeGen/X86/sse41-blend.ll
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=139528&r1=139527&r2=139528&view=diff
>
==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Sep 12 14:30:40 2011
> @@ -8445,16 +8445,25 @@
> unsigned Opc = EltVT == MVT::f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
> bool Swap = false;
>
> + // SSE Condition code mapping:
> + // 0 - EQ
> + // 1 - LT
> + // 2 - LE
> + // 3 - UNORD
> + // 4 - NEQ
> + // 5 - NLT
> + // 6 - NLE
> + // 7 - ORD
> switch (SetCCOpcode) {
> default: break;
> case ISD::SETOEQ:
> case ISD::SETEQ: SSECC = 0; break;
> - case ISD::SETOGT:
> - case ISD::SETGT: Swap = true; // Fallthrough
> - case ISD::SETLT:
> - case ISD::SETOLT: SSECC = 1; break;
> case ISD::SETOGE:
> case ISD::SETGE: Swap = true; // Fallthrough
> + case ISD::SETLT:
> + case ISD::SETOLT: SSECC = 1; break;
> + case ISD::SETOGT:
> + case ISD::SETGT: Swap = true; // Fallthrough
> case ISD::SETLE:
> case ISD::SETOLE: SSECC = 2; break;
> case ISD::SETUO: SSECC = 3; break;
> @@ -8473,20 +8482,20 @@
> if (SSECC == 8) {
> if (SetCCOpcode == ISD::SETUEQ) {
> SDValue UNORD, EQ;
> - UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3,
MVT::i8));
> - EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0,
MVT::i8));
> + UNORD = DAG.getNode(Opc, dl, VT, Op1, Op0, DAG.getConstant(3,
MVT::i8));
> + EQ = DAG.getNode(Opc, dl, VT, Op1, Op0, DAG.getConstant(0,
MVT::i8));
> return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
> }
> else if (SetCCOpcode == ISD::SETONE) {
> SDValue ORD, NEQ;
> - ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7,
MVT::i8));
> - NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4,
MVT::i8));
> + ORD = DAG.getNode(Opc, dl, VT, Op1, Op0, DAG.getConstant(7,
MVT::i8));
> + NEQ = DAG.getNode(Opc, dl, VT, Op1, Op0, DAG.getConstant(4,
MVT::i8));
> return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
> }
> llvm_unreachable("Illegal FP comparison");
> }
> // Handle all other FP comparisons here.
> - return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC,
MVT::i8));
> + return DAG.getNode(Opc, dl, VT, Op1, Op0, DAG.getConstant(SSECC,
MVT::i8));
> }
>
> // Break 256-bit integer vector compare into smaller ones.
>
> Modified: llvm/trunk/test/CodeGen/X86/avx-blend.ll
> URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-blend.ll?rev=139528&r1=139527&r2=139528&view=diff
>
==============================================================================
> --- llvm/trunk/test/CodeGen/X86/avx-blend.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/avx-blend.ll Mon Sep 12 14:30:40 2011
> @@ -82,4 +82,23 @@
> ret <8 x i64> %vsel
> }
>
> +;; TEST blend + compares
> +; CHECK: A
> +define <2 x double> @A(<2 x double> %x, <2 x double> %y) {
> + ; CHECK: vcmpltpd
> + ; CHECK: vblendvpd
> + %max_is_x = fcmp oge <2 x double> %x, %y
> + %max = select <2 x i1> %max_is_x, <2 x double> %x, <2 x double> %y
> + ret <2 x double> %max
> +}
> +
> +; CHECK: B
> +define <2 x double> @B(<2 x double> %x, <2 x double> %y) {
> + ; CHECK: vcmplepd
> + ; CHECK: vblendvpd
> + %max_is_x = fcmp ogt <2 x double> %x, %y
> + %max = select <2 x i1> %max_is_x, <2 x double> %x, <2 x double> %y
> + ret <2 x double> %max
> +}
> +
>
>
> Modified: llvm/trunk/test/CodeGen/X86/sse41-blend.ll
> URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse41-blend.ll?rev=139528&r1=139527&r2=139528&view=diff
>
==============================================================================
> --- llvm/trunk/test/CodeGen/X86/sse41-blend.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/sse41-blend.ll Mon Sep 12 14:30:40 2011
> @@ -44,4 +44,22 @@
> ret <16 x i8> %vsel
> }
>
> +;; TEST blend + compares
> +; CHECK: A
> +define <2 x double> @A(<2 x double> %x, <2 x double> %y) {
> + ; CHECK: cmpltpd
> + ; CHECK: blendvpd
> + %max_is_x = fcmp oge <2 x double> %x, %y
> + %max = select <2 x i1> %max_is_x, <2 x double> %x, <2 x double> %y
> + ret <2 x double> %max
> +}
> +
> +; CHECK: B
> +define <2 x double> @B(<2 x double> %x, <2 x double> %y) {
> + ; CHECK: cmplepd
> + ; CHECK: blendvpd
> + %max_is_x = fcmp ogt <2 x double> %x, %y
> + %max = select <2 x i1> %max_is_x, <2 x double> %x, <2 x double> %y
> + ret <2 x double> %max
> +}
>
>
>
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--
Bruno Cardoso Lopes
http://www.brunocardoso.cc
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