This is actually wrong, will commit a fix soon<br><br>On Monday, September 12, 2011, Bruno Cardoso Lopes <<a href="mailto:bruno.cardoso@gmail.com">bruno.cardoso@gmail.com</a>> wrote:<br>> Author: bruno<br>> Date: Mon Sep 12 14:30:40 2011<br>
> New Revision: 139528<br>><br>> URL: <a href="http://llvm.org/viewvc/llvm-project?rev=139528&view=rev">http://llvm.org/viewvc/llvm-project?rev=139528&view=rev</a><br>> Log:<br>> Not sure how CMPPS and CMPPD had already ever worked, I guess it didn't.<br>
> However with this fix it does now.<br>><br>> Basically the operand order for the x86 target specific node<br>> is not the same as the instruction, but since the intrinsic need that<br>> specific order at the instruction definition, just change the order<br>
> during legalization. Also, there were some wrong invertions of condition<br>> codes, such as GE => LE, GT => LT, fix that too. Fix PR10907.<br>><br>> Modified:<br>> llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
> llvm/trunk/test/CodeGen/X86/avx-blend.ll<br>> llvm/trunk/test/CodeGen/X86/sse41-blend.ll<br>><br>> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=139528&r1=139527&r2=139528&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=139528&r1=139527&r2=139528&view=diff</a><br>
> ==============================================================================<br>> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)<br>> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Sep 12 14:30:40 2011<br>
> @@ -8445,16 +8445,25 @@<br>> unsigned Opc = EltVT == MVT::f32 ? X86ISD::CMPPS : X86ISD::CMPPD;<br>> bool Swap = false;<br>><br>> + // SSE Condition code mapping:<br>> + // 0 - EQ<br>> + // 1 - LT<br>
> + // 2 - LE<br>> + // 3 - UNORD<br>> + // 4 - NEQ<br>> + // 5 - NLT<br>> + // 6 - NLE<br>> + // 7 - ORD<br>> switch (SetCCOpcode) {<br>> default: break;<br>> case ISD::SETOEQ:<br>
> case ISD::SETEQ: SSECC = 0; break;<br>> - case ISD::SETOGT:<br>> - case ISD::SETGT: Swap = true; // Fallthrough<br>> - case ISD::SETLT:<br>> - case ISD::SETOLT: SSECC = 1; break;<br>> case ISD::SETOGE:<br>
> case ISD::SETGE: Swap = true; // Fallthrough<br>> + case ISD::SETLT:<br>> + case ISD::SETOLT: SSECC = 1; break;<br>> + case ISD::SETOGT:<br>> + case ISD::SETGT: Swap = true; // Fallthrough<br>
> case ISD::SETLE:<br>> case ISD::SETOLE: SSECC = 2; break;<br>> case ISD::SETUO: SSECC = 3; break;<br>> @@ -8473,20 +8482,20 @@<br>> if (SSECC == 8) {<br>> if (SetCCOpcode == ISD::SETUEQ) {<br>
> SDValue UNORD, EQ;<br>> - UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));<br>> - EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));<br>> + UNORD = DAG.getNode(Opc, dl, VT, Op1, Op0, DAG.getConstant(3, MVT::i8));<br>
> + EQ = DAG.getNode(Opc, dl, VT, Op1, Op0, DAG.getConstant(0, MVT::i8));<br>> return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);<br>> }<br>> else if (SetCCOpcode == ISD::SETONE) {<br>> SDValue ORD, NEQ;<br>
> - ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));<br>> - NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));<br>> + ORD = DAG.getNode(Opc, dl, VT, Op1, Op0, DAG.getConstant(7, MVT::i8));<br>
> + NEQ = DAG.getNode(Opc, dl, VT, Op1, Op0, DAG.getConstant(4, MVT::i8));<br>> return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);<br>> }<br>> llvm_unreachable("Illegal FP comparison");<br>
> }<br>> // Handle all other FP comparisons here.<br>> - return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));<br>> + return DAG.getNode(Opc, dl, VT, Op1, Op0, DAG.getConstant(SSECC, MVT::i8));<br>
> }<br>><br>> // Break 256-bit integer vector compare into smaller ones.<br>><br>> Modified: llvm/trunk/test/CodeGen/X86/avx-blend.ll<br>> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-blend.ll?rev=139528&r1=139527&r2=139528&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-blend.ll?rev=139528&r1=139527&r2=139528&view=diff</a><br>
> ==============================================================================<br>> --- llvm/trunk/test/CodeGen/X86/avx-blend.ll (original)<br>> +++ llvm/trunk/test/CodeGen/X86/avx-blend.ll Mon Sep 12 14:30:40 2011<br>
> @@ -82,4 +82,23 @@<br>> ret <8 x i64> %vsel<br>> }<br>><br>> +;; TEST blend + compares<br>> +; CHECK: A<br>> +define <2 x double> @A(<2 x double> %x, <2 x double> %y) {<br>
> + ; CHECK: vcmpltpd<br>> + ; CHECK: vblendvpd<br>> + %max_is_x = fcmp oge <2 x double> %x, %y<br>> + %max = select <2 x i1> %max_is_x, <2 x double> %x, <2 x double> %y<br>> + ret <2 x double> %max<br>
> +}<br>> +<br>> +; CHECK: B<br>> +define <2 x double> @B(<2 x double> %x, <2 x double> %y) {<br>> + ; CHECK: vcmplepd<br>> + ; CHECK: vblendvpd<br>> + %max_is_x = fcmp ogt <2 x double> %x, %y<br>
> + %max = select <2 x i1> %max_is_x, <2 x double> %x, <2 x double> %y<br>> + ret <2 x double> %max<br>> +}<br>> +<br>><br>><br>> Modified: llvm/trunk/test/CodeGen/X86/sse41-blend.ll<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse41-blend.ll?rev=139528&r1=139527&r2=139528&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse41-blend.ll?rev=139528&r1=139527&r2=139528&view=diff</a><br>
> ==============================================================================<br>> --- llvm/trunk/test/CodeGen/X86/sse41-blend.ll (original)<br>> +++ llvm/trunk/test/CodeGen/X86/sse41-blend.ll Mon Sep 12 14:30:40 2011<br>
> @@ -44,4 +44,22 @@<br>> ret <16 x i8> %vsel<br>> }<br>><br>> +;; TEST blend + compares<br>> +; CHECK: A<br>> +define <2 x double> @A(<2 x double> %x, <2 x double> %y) {<br>
> + ; CHECK: cmpltpd<br>> + ; CHECK: blendvpd<br>> + %max_is_x = fcmp oge <2 x double> %x, %y<br>> + %max = select <2 x i1> %max_is_x, <2 x double> %x, <2 x double> %y<br>> + ret <2 x double> %max<br>
> +}<br>> +<br>> +; CHECK: B<br>> +define <2 x double> @B(<2 x double> %x, <2 x double> %y) {<br>> + ; CHECK: cmplepd<br>> + ; CHECK: blendvpd<br>> + %max_is_x = fcmp ogt <2 x double> %x, %y<br>
> + %max = select <2 x i1> %max_is_x, <2 x double> %x, <2 x double> %y<br>> + ret <2 x double> %max<br>> +}<br>><br>><br>><br>> _______________________________________________<br>
> llvm-commits mailing list<br>> <a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br>> <a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits">http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</a><br>
><br><br>-- <br>Bruno Cardoso Lopes <br><a href="http://www.brunocardoso.cc">http://www.brunocardoso.cc</a><br>