[llvm-commits] [PATCH] Fix cortex-m class MSR/MRS and resolve (safe) ambiguous instruction encodings

[James Molloy]

Owen,

I don't have the ISA reference in front of me right now (not at work), but IIRC the problem was less that the encoding was wrong and more that there wasn't a Thumb2 STC instruction node at all, only an ARM-mode one.

Therefore it failed to decode now that the predicate checks are correctly in place. Creating a t2STC2 insn node is the answer to fix it, but I didn't want to stuff everything into one patch. I can fix that as a followup.

James
________________________________________
From: Owen Anderson [resistor at me.com]
Sent: 06 September 2011 21:44
To: James Molloy
Cc: llvm-commits at cs.uiuc.edu
Subject: Re: [llvm-commits] [PATCH] Fix cortex-m class MSR/MRS and resolve      (safe) ambiguous instruction encodings

James,

On Sep 2, 2011, at 8:38 AM, James Molloy wrote:
> **As part of this, a bug in the MC was found in that ARM-mode STC2's were being
> generated in Thumb2 mode (not the T2 encoding) and the test was checking for
> this. The test has been disabled for the moment until a patch to add T2 STC/STC2
> is created.**

What exactly is the issue with STC's?  My copy of the ISA reference shows the encoding being the same for ARM and Thumb2 modes, other than the lack of a predicate operand in Thumb2 mode.

--Owen



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