[llvm-commits] [PATCH] Fix cortex-m class MSR/MRS and resolve (safe) ambiguous instruction encodings

[Owen Anderson]

James,

On Sep 2, 2011, at 8:38 AM, James Molloy wrote:
> **As part of this, a bug in the MC was found in that ARM-mode STC2's were being
> generated in Thumb2 mode (not the T2 encoding) and the test was checking for
> this. The test has been disabled for the moment until a patch to add T2 STC/STC2
> is created.**

What exactly is the issue with STC's?  My copy of the ISA reference shows the encoding being the same for ARM and Thumb2 modes, other than the lack of a predicate operand in Thumb2 mode.

--Owen