[llvm-commits] [llvm] r138338 - in /llvm/trunk/lib/Target/ARM: ARMBaseInstrInfo.cpp ARMInstrThumb.td InstPrinter/ARMInstPrinter.cpp
Jim Grosbach
grosbach at apple.com
Tue Aug 23 10:41:15 PDT 2011
Author: grosbach
Date: Tue Aug 23 12:41:15 2011
New Revision: 138338
URL: http://llvm.org/viewvc/llvm-project?rev=138338&view=rev
Log:
Clean up Thumb load/store multiple definitions.
There is no non-writeback store multiple instruction in Thumb1, so
don't define one. As a result load multiple is the only instantiation of
the multiclass, so refactor that away entirely.
Modified:
llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=138338&r1=138337&r2=138338&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Tue Aug 23 12:41:15 2011
@@ -1930,7 +1930,6 @@
case ARM::STMIB_UPD:
case ARM::tLDMIA:
case ARM::tLDMIA_UPD:
- case ARM::tSTMIA:
case ARM::tSTMIA_UPD:
case ARM::tPOP_RET:
case ARM::tPOP:
@@ -2196,7 +2195,6 @@
case ARM::STMDA_UPD:
case ARM::STMDB_UPD:
case ARM::STMIB_UPD:
- case ARM::tSTMIA:
case ARM::tSTMIA_UPD:
case ARM::tPOP_RET:
case ARM::tPOP:
Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=138338&r1=138337&r2=138338&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Tue Aug 23 12:41:15 2011
@@ -694,44 +694,45 @@
// Load / store multiple Instructions.
//
-multiclass thumb_ldst_mult<string asm, InstrItinClass itin,
- InstrItinClass itin_upd, bits<6> T1Enc,
- bit L_bit, string baseOpc> {
- def IA :
- T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
- itin, !strconcat(asm, "${p}\t$Rn, $regs"), []>,
- T1Encoding<T1Enc> {
- bits<3> Rn;
- bits<8> regs;
- let Inst{10-8} = Rn;
- let Inst{7-0} = regs;
- }
-
- def IA_UPD :
- InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain,
- "$Rn = $wb", itin_upd>,
- PseudoInstExpansion<(!cast<Instruction>(!strconcat(baseOpc, "IA"))
- tGPR:$Rn, pred:$p, reglist:$regs)> {
- let Size = 2;
- let OutOperandList = (outs GPR:$wb);
- let InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
- let Pattern = [];
- let isCodeGenOnly = 1;
- let isPseudo = 1;
- list<Predicate> Predicates = [IsThumb];
- }
-}
-
// These require base address to be written back or one of the loaded regs.
let neverHasSideEffects = 1 in {
let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
-defm tLDM : thumb_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu,
- {1,1,0,0,1,?}, 1, "tLDM">;
+def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
+ IIC_iLoad_m, "ldm${p}\t$Rn, $regs", []>, T1Encoding<{1,1,0,0,1,?}> {
+ bits<3> Rn;
+ bits<8> regs;
+ let Inst{10-8} = Rn;
+ let Inst{7-0} = regs;
+}
+
+// Writeback version is just a pseudo, as there's no encoding difference.
+// Writeback happens iff the base register is not in the destination register
+// list.
+def tLDMIA_UPD :
+ InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain,
+ "$Rn = $wb", IIC_iLoad_mu>,
+ PseudoInstExpansion<(tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)> {
+ let Size = 2;
+ let OutOperandList = (outs GPR:$wb);
+ let InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
+ let Pattern = [];
+ let isCodeGenOnly = 1;
+ let isPseudo = 1;
+ list<Predicate> Predicates = [IsThumb];
+}
+// There is no non-writeback version of STM for Thumb.
let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
-defm tSTM : thumb_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu,
- {1,1,0,0,0,?}, 0, "tSTM">;
+def tSTMIA_UPD : T1I<(outs),
+ (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
+ IIC_iStore_mu, "stm${p}\t$Rn!, $regs", []>,
+ T1Encoding<{1,1,0,0,0,?}> {
+ bits<3> Rn;
+ bits<8> regs;
+ let Inst{10-8} = Rn;
+ let Inst{7-0} = regs;
+}
} // neverHasSideEffects
@@ -739,7 +740,6 @@
(tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)>,
Requires<[IsThumb, IsThumb1Only]>;
-
let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
IIC_iPop,
@@ -1147,8 +1147,6 @@
"sub", "\t$Rd, $Rn, $Rm",
[(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>;
-// TODO: A7-96: STMIA - store multiple.
-
// Sign-extend byte
def tSXTB : // A8.6.222
T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=138338&r1=138337&r2=138338&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Tue Aug 23 12:41:15 2011
@@ -146,7 +146,7 @@
return;
}
- if (Opcode == ARM::tLDMIA || Opcode == ARM::tSTMIA) {
+ if (Opcode == ARM::tLDMIA) {
bool Writeback = true;
unsigned BaseReg = MI->getOperand(0).getReg();
for (unsigned i = 3; i < MI->getNumOperands(); ++i) {
@@ -154,12 +154,7 @@
Writeback = false;
}
- if (Opcode == ARM::tLDMIA)
- O << "\tldm";
- else if (Opcode == ARM::tSTMIA)
- O << "\tstm";
- else
- llvm_unreachable("Unknown opcode!");
+ O << "\tldm";
printPredicateOperand(MI, 1, O);
O << '\t' << getRegisterName(BaseReg);
More information about the llvm-commits
mailing list