[llvm-commits] [llvm] r137310 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

[Rotem, Nadav]

Hi Bruno, 

The pattern appears because of a shuffle (<4 5 6 7, 0 1 2 3>) on our local branch. I tried to reproduce this on ToT but it created scalar code. I will continue to look for a pattern and if I don't find one I will remove the code. 

Thanks for reviewing my patches!

-Nadav

-----Original Message-----
From: Bruno Cardoso Lopes [mailto:bruno.cardoso at gmail.com] 
Sent: Thursday, August 11, 2011 20:01
To: Rotem, Nadav
Cc: llvm-commits at cs.uiuc.edu
Subject: Re: [llvm-commits] [llvm] r137310 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Hi,

Nice! Can you please add the testcase that triggered this DAGCombine?
Thanks!

On Thu, Aug 11, 2011 at 9:49 AM, Nadav Rotem <nadav.rotem at intel.com> wrote:
> Author: nadav
> Date: Thu Aug 11 11:49:36 2011
> New Revision: 137310
>
> URL: http://llvm.org/viewvc/llvm-project?rev=137310&view=rev
> Log:
> [AVX] When joining  two XMM registers into a YMM register, make sure that the
> lower XMM register gets in first. This will allow the SUBREG pattern to
> elliminate the first vector insertion.
>
>
> Modified:
>    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=137310&r1=137309&r2=137310&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Aug 11 11:49:36 2011
> @@ -213,6 +213,7 @@
>     SDValue visitLOAD(SDNode *N);
>     SDValue visitSTORE(SDNode *N);
>     SDValue visitINSERT_VECTOR_ELT(SDNode *N);
> +    SDValue visitINSERT_SUBVECTOR(SDNode *N);
>     SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
>     SDValue visitBUILD_VECTOR(SDNode *N);
>     SDValue visitCONCAT_VECTORS(SDNode *N);
> @@ -1102,6 +1103,7 @@
>   case ISD::LOAD:               return visitLOAD(N);
>   case ISD::STORE:              return visitSTORE(N);
>   case ISD::INSERT_VECTOR_ELT:  return visitINSERT_VECTOR_ELT(N);
> +  case ISD::INSERT_SUBVECTOR:  return visitINSERT_SUBVECTOR(N);
>   case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
>   case ISD::BUILD_VECTOR:       return visitBUILD_VECTOR(N);
>   case ISD::CONCAT_VECTORS:     return visitCONCAT_VECTORS(N);
> @@ -7136,6 +7138,36 @@
>   }
>  }
>
> +SDValue DAGCombiner::visitINSERT_SUBVECTOR(SDNode* N) {
> +  DebugLoc dl = N->getDebugLoc();
> +  EVT VT = N->getValueType(0);
> +  // When inserting a subvector into a vector, make sure to start
> +  // inserting starting the Zero index. This will allow making the
> +  // first insertion using a subreg insertion, and save a register.
> +  SDValue V = N->getOperand(0);
> +  if (V->getOpcode() == ISD::INSERT_SUBVECTOR && V->hasOneUse()) {
> +    ConstantSDNode *N_Idx = dyn_cast<ConstantSDNode>(N->getOperand(2));
> +    ConstantSDNode *V_Idx = dyn_cast<ConstantSDNode>(V->getOperand(2));
> +    uint64_t Nc = N_Idx->getZExtValue();
> +    uint64_t Vc = V_Idx->getZExtValue();
> +
> +    // Reorder insertion to vector
> +    if (Nc < Vc) {
> +      SDValue NewV = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, VT,
> +                                 V->getOperand(0),
> +                                 N->getOperand(1),
> +                                 N->getOperand(2));
> +      return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, VT,
> +                         NewV,
> +                         V->getOperand(1),
> +                         V->getOperand(2));
> +    }
> +  }
> +
> +  return SDValue();
> +}
> +
> +
>  /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
>  /// an AND to a vector_shuffle with the destination vector and a zero vector.
>  /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
>
>
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-- 
Bruno Cardoso Lopes
http://www.brunocardoso.cc
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