[llvm-commits] [PATCH] ARMDisassembler: Fix disassembly of shift immediates

[James Molloy]

Hi,

 

The ARM disassembler  incorrectly disassembles an instruction with a shift
LSR or ASR with immediate #32 as #0. The ARMARM (manual v7AR section 8.4.1)
states the LSR/ASR have immediate in the range 1-32 inclusive.

 

The attached (and inlined) patch fixes this behaviour by addition of a
helper function, and adds a  testcase.

 

Cheers,

 

James

 

Index: test/MC/Disassembler/ARM/arm-tests.txt

===================================================================

--- test/MC/Disassembler/ARM/arm-tests.txt      (revision 137305)

+++ test/MC/Disassembler/ARM/arm-tests.txt      (working copy)

@@ -302,3 +302,6 @@

 

# CHECK:       nop

0x00 0xf0 0x20 0xe3

+

+# CHECK:        andeq   r0, r0, r0, lsr #32

+0x20 0x00 0x00 0x00

Index: lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp

===================================================================

--- lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp       (revision 137305)

+++ lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp       (working copy)

@@ -25,6 +25,16 @@

#define GET_INSTRUCTION_NAME

#include "ARMGenAsmWriter.inc"

 

+/// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for
printing.

+///

+/// getSORegOffset returns an integer from 0-31, but '0' should actually be
printed

+/// 32 as the immediate shouldbe within the range 1-32.

+static unsigned translateShiftImm(unsigned imm) {

+  if (imm == 0)

+    return 32;

+  return imm;

+}

+

StringRef ARMInstPrinter::getOpcodeName(unsigned Opcode) const {

   return getInstructionName(Opcode);

}

@@ -72,7 +82,7 @@

     if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx)

       return;

 

-    O << ", #" << ARM_AM::getSORegOffset(MO2.getImm());

+    O << ", #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));

     return;

   }

 

@@ -196,7 +206,7 @@

   O << ", " << ARM_AM::getShiftOpcStr(ShOpc);

   if (ShOpc == ARM_AM::rrx)

     return;

-  O << " #" << ARM_AM::getSORegOffset(MO2.getImm());

+  O << " #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));

}

 

 

@@ -707,7 +717,7 @@

   ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());

   O << ", " << ARM_AM::getShiftOpcStr(ShOpc);

   if (ShOpc != ARM_AM::rrx)

-    O << " #" << ARM_AM::getSORegOffset(MO2.getImm());

+    O << " #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));

}

 

void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned
OpNum,

 

 
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