[llvm-commits] [llvm] r134678 - in /llvm/trunk: include/llvm/Target/ lib/CodeGen/ lib/CodeGen/AsmPrinter/ lib/MC/MCDisassembler/ lib/Target/ lib/Target/ARM/ lib/Target/ARM/AsmParser/ lib/Target/ARM/MCTargetDesc/ lib/Target/Alpha/ lib/Target/Black
Evan Cheng
evan.cheng at apple.com
Thu Jul 7 20:36:36 PDT 2011
Thanks. Sorry I forgot to commit the clang change. :-(
Evan
On Jul 7, 2011, at 8:16 PM, Chandler Carruth wrote:
> Fixed in r134680.
>
> On Thu, Jul 7, 2011 at 7:39 PM, Nick Lewycky <nlewycky at google.com> wrote:
> Hi Evan, is there a clang half to this change that's coming shortly?
>
> nlewycky at ducttape:~/llvm/tools/clang/tools/driver$ make
> llvm[0]: Compiling cc1as_main.cpp for Debug+Asserts build
> cc1as_main.cpp: In function ‘bool ExecuteAssembler(<unnamed>::AssemblerInvocation&, clang::Diagnostic&)’:
> cc1as_main.cpp:311: error: no matching function for call to ‘llvm::Target::createAsmParser(llvm::MCAsmParser&, llvm::TargetMachine&) const’
> /usr/local/google/home/nlewycky/llvm/include/llvm/Target/TargetRegistry.h:302: note: candidates are: llvm::TargetAsmParser* llvm::Target::createAsmParser(llvm::StringRef, llvm::StringRef, llvm::StringRef, llvm::MCAsmParser&) const
> make: *** [/usr/local/google/home/nlewycky/llvm/tools/clang/tools/driver/Debug+Asserts/cc1as_main.o] Error 1
>
> Nick
>
> On 7 July 2011 18:53, Evan Cheng <evan.cheng at apple.com> wrote:
> Author: evancheng
> Date: Thu Jul 7 20:53:10 2011
> New Revision: 134678
>
> URL: http://llvm.org/viewvc/llvm-project?rev=134678&view=rev
> Log:
> Eliminate asm parser's dependency on TargetMachine:
> - Each target asm parser now creates its own MCSubtatgetInfo (if needed).
> - Changed AssemblerPredicate to take subtarget features which tablegen uses
> to generate asm matcher subtarget feature queries. e.g.
> "ModeThumb,FeatureThumb2" is translated to
> "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".
>
> Modified:
> llvm/trunk/include/llvm/Target/Target.td
> llvm/trunk/include/llvm/Target/TargetMachine.h
> llvm/trunk/include/llvm/Target/TargetRegistry.h
> llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
> llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
> llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp
> llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.h
> llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
> llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
> llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
> llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
> llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
> llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h
> llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp
> llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp
> llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp
> llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp
> llvm/trunk/lib/Target/CBackend/CTargetMachine.h
> llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp
> llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp
> llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h
> llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp
> llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp
> llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp
> llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp
> llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp
> llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp
> llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp
> llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp
> llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp
> llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp
> llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp
> llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp
> llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp
> llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp
> llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp
> llvm/trunk/lib/Target/TargetMachine.cpp
> llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp
> llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
> llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h
> llvm/trunk/lib/Target/X86/X86InstrInfo.td
> llvm/trunk/lib/Target/X86/X86Subtarget.cpp
> llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
> llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp
> llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp
> llvm/trunk/tools/llvm-mc/llvm-mc.cpp
> llvm/trunk/tools/lto/LTOModule.cpp
> llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp
> llvm/trunk/utils/TableGen/SubtargetEmitter.cpp
>
> Modified: llvm/trunk/include/llvm/Target/Target.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Target.td?rev=134678&r1=134677&r2=134678&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/Target/Target.td (original)
> +++ llvm/trunk/include/llvm/Target/Target.td Thu Jul 7 20:53:10 2011
> @@ -382,6 +382,15 @@
> /// matcher, this is true. Targets should set this by inheriting their
> /// feature from the AssemblerPredicate class in addition to Predicate.
> bit AssemblerMatcherPredicate = 0;
> +
> + /// AssemblerCondString - Name of the subtarget feature being tested used
> + /// as alternative condition string used for assembler matcher.
> + /// e.g. "ModeThumb" is translated to "(Bits & ModeThumb) != 0".
> + /// "!ModeThumb" is translated to "(Bits & ModeThumb) == 0".
> + /// It can also list multiple features separated by ",".
> + /// e.g. "ModeThumb,FeatureThumb2" is translated to
> + /// "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".
> + string AssemblerCondString = "";
> }
>
> /// NoHonorSignDependentRounding - This predicate is true if support for
> @@ -689,8 +698,9 @@
>
> /// AssemblerPredicate - This is a Predicate that can be used when the assembler
> /// matches instructions and aliases.
> -class AssemblerPredicate {
> +class AssemblerPredicate<string cond> {
> bit AssemblerMatcherPredicate = 1;
> + string AssemblerCondString = cond;
> }
>
>
>
> Modified: llvm/trunk/include/llvm/Target/TargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetMachine.h?rev=134678&r1=134677&r2=134678&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/Target/TargetMachine.h (original)
> +++ llvm/trunk/include/llvm/Target/TargetMachine.h Thu Jul 7 20:53:10 2011
> @@ -14,6 +14,7 @@
> #ifndef LLVM_TARGET_TARGETMACHINE_H
> #define LLVM_TARGET_TARGETMACHINE_H
>
> +#include "llvm/ADT/StringRef.h"
> #include <cassert>
> #include <string>
>
> @@ -91,7 +92,8 @@
> TargetMachine(const TargetMachine &); // DO NOT IMPLEMENT
> void operator=(const TargetMachine &); // DO NOT IMPLEMENT
> protected: // Can only create subclasses.
> - TargetMachine(const Target &);
> + TargetMachine(const Target &T, StringRef TargetTriple,
> + StringRef CPU, StringRef FS);
>
> /// getSubtargetImpl - virtual method implemented by subclasses that returns
> /// a reference to that target's TargetSubtargetInfo-derived member variable.
> @@ -100,6 +102,12 @@
> /// TheTarget - The Target that this machine was created for.
> const Target &TheTarget;
>
> + /// TargetTriple, TargetCPU, TargetFS - Triple string, CPU name, and target
> + /// feature strings the TargetMachine instance is created with.
> + std::string TargetTriple;
> + std::string TargetCPU;
> + std::string TargetFS;
> +
> /// AsmInfo - Contains target specific asm information.
> ///
> const MCAsmInfo *AsmInfo;
> @@ -115,6 +123,10 @@
>
> const Target &getTarget() const { return TheTarget; }
>
> + const StringRef getTargetTriple() const { return TargetTriple; }
> + const StringRef getTargetCPU() const { return TargetCPU; }
> + const StringRef getTargetFeatureString() const { return TargetFS; }
> +
> // Interfaces to the major aspects of target machine information:
> // -- Instruction opcode and operand information
> // -- Pipelines and scheduling information
> @@ -295,10 +307,9 @@
> /// implemented with the LLVM target-independent code generator.
> ///
> class LLVMTargetMachine : public TargetMachine {
> - std::string TargetTriple;
> -
> protected: // Can only create subclasses.
> - LLVMTargetMachine(const Target &T, const std::string &TargetTriple);
> + LLVMTargetMachine(const Target &T, StringRef TargetTriple,
> + StringRef CPU, StringRef FS);
>
> private:
> /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
> @@ -311,9 +322,6 @@
> virtual void setCodeModelForStatic();
>
> public:
> -
> - const std::string &getTargetTriple() const { return TargetTriple; }
> -
> /// addPassesToEmitFile - Add passes to the specified pass manager to get the
> /// specified file emitted. Typically this will involve several steps of code
> /// generation. If OptLevel is None, the code generator should emit code as
>
> Modified: llvm/trunk/include/llvm/Target/TargetRegistry.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegistry.h?rev=134678&r1=134677&r2=134678&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/Target/TargetRegistry.h (original)
> +++ llvm/trunk/include/llvm/Target/TargetRegistry.h Thu Jul 7 20:53:10 2011
> @@ -35,7 +35,6 @@
> class MCInstPrinter;
> class MCInstrInfo;
> class MCRegisterInfo;
> - class MCSubtargetInfo;
> class MCStreamer;
> class TargetAsmBackend;
> class TargetAsmLexer;
> @@ -70,9 +69,6 @@
> StringRef TT);
> typedef MCInstrInfo *(*MCInstrInfoCtorFnTy)(void);
> typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(void);
> - typedef MCSubtargetInfo *(*MCSubtargetInfoCtorFnTy)(StringRef TT,
> - StringRef CPU,
> - StringRef Features);
> typedef TargetMachine *(*TargetMachineCtorTy)(const Target &T,
> const std::string &TT,
> const std::string &CPU,
> @@ -83,8 +79,9 @@
> const std::string &TT);
> typedef TargetAsmLexer *(*AsmLexerCtorTy)(const Target &T,
> const MCAsmInfo &MAI);
> - typedef TargetAsmParser *(*AsmParserCtorTy)(const Target &T,MCAsmParser &P,
> - TargetMachine &TM);
> + typedef TargetAsmParser *(*AsmParserCtorTy)(const Target &T, StringRef TT,
> + StringRef CPU, StringRef Features,
> + MCAsmParser &P);
> typedef MCDisassembler *(*MCDisassemblerCtorTy)(const Target &T);
> typedef MCInstPrinter *(*MCInstPrinterCtorTy)(const Target &T,
> unsigned SyntaxVariant,
> @@ -140,10 +137,6 @@
> /// if registered.
> MCRegInfoCtorFnTy MCRegInfoCtorFn;
>
> - /// MCSubtargetInfoCtorFn - Constructor function for this target's
> - /// MCSubtargetInfo, if registered.
> - MCSubtargetInfoCtorFnTy MCSubtargetInfoCtorFn;
> -
> /// TargetMachineCtorFn - Construction function for this target's
> /// TargetMachine, if registered.
> TargetMachineCtorTy TargetMachineCtorFn;
> @@ -269,22 +262,6 @@
> return MCRegInfoCtorFn();
> }
>
> - /// createMCSubtargetInfo - Create a MCSubtargetInfo implementation.
> - ///
> - /// \arg Triple - This argument is used to determine the target machine
> - /// feature set; it should always be provided. Generally this should be
> - /// either the target triple from the module, or the target triple of the
> - /// host if that does not exist.
> - /// \arg CPU - This specifies the name of the target CPU.
> - /// \arg Features - This specifies the string representation of the
> - /// additional target features.
> - MCSubtargetInfo *createMCSubtargetInfo(StringRef Triple, StringRef CPU,
> - StringRef Features) const {
> - if (!MCSubtargetInfoCtorFn)
> - return 0;
> - return MCSubtargetInfoCtorFn(Triple, CPU, Features);
> - }
> -
> /// createTargetMachine - Create a target specific machine implementation
> /// for the specified \arg Triple.
> ///
> @@ -322,11 +299,11 @@
> ///
> /// \arg Parser - The target independent parser implementation to use for
> /// parsing and lexing.
> - TargetAsmParser *createAsmParser(MCAsmParser &Parser,
> - TargetMachine &TM) const {
> + TargetAsmParser *createAsmParser(StringRef Triple, StringRef CPU,
> + StringRef Features, MCAsmParser &Parser) const {
> if (!AsmParserCtorFn)
> return 0;
> - return AsmParserCtorFn(*this, Parser, TM);
> + return AsmParserCtorFn(*this, Triple, CPU, Features, Parser);
> }
>
> /// createAsmPrinter - Create a target specific assembly printer pass. This
> @@ -528,22 +505,6 @@
> T.MCRegInfoCtorFn = Fn;
> }
>
> - /// RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for
> - /// the given target.
> - ///
> - /// Clients are responsible for ensuring that registration doesn't occur
> - /// while another thread is attempting to access the registry. Typically
> - /// this is done by initializing all targets at program startup.
> - ///
> - /// @param T - The target being registered.
> - /// @param Fn - A function to construct a MCSubtargetInfo for the target.
> - static void RegisterMCSubtargetInfo(Target &T,
> - Target::MCSubtargetInfoCtorFnTy Fn) {
> - // Ignore duplicate registration.
> - if (!T.MCSubtargetInfoCtorFn)
> - T.MCSubtargetInfoCtorFn = Fn;
> - }
> -
> /// RegisterTargetMachine - Register a TargetMachine implementation for the
> /// given target.
> ///
> @@ -820,40 +781,6 @@
> }
> };
>
> - /// RegisterMCSubtargetInfo - Helper template for registering a target
> - /// subtarget info implementation. This invokes the static "Create" method
> - /// on the class to actually do the construction. Usage:
> - ///
> - /// extern "C" void LLVMInitializeFooTarget() {
> - /// extern Target TheFooTarget;
> - /// RegisterMCSubtargetInfo<FooMCSubtargetInfo> X(TheFooTarget);
> - /// }
> - template<class MCSubtargetInfoImpl>
> - struct RegisterMCSubtargetInfo {
> - RegisterMCSubtargetInfo(Target &T) {
> - TargetRegistry::RegisterMCSubtargetInfo(T, &Allocator);
> - }
> - private:
> - static MCSubtargetInfo *Allocator(StringRef TT, StringRef CPU,
> - StringRef FS) {
> - return new MCSubtargetInfoImpl();
> - }
> - };
> -
> - /// RegisterMCSubtargetInfoFn - Helper template for registering a target
> - /// subtarget info implementation. This invokes the specified function to
> - /// do the construction. Usage:
> - ///
> - /// extern "C" void LLVMInitializeFooTarget() {
> - /// extern Target TheFooTarget;
> - /// RegisterMCSubtargetInfoFn X(TheFooTarget, TheFunction);
> - /// }
> - struct RegisterMCSubtargetInfoFn {
> - RegisterMCSubtargetInfoFn(Target &T, Target::MCSubtargetInfoCtorFnTy Fn) {
> - TargetRegistry::RegisterMCSubtargetInfo(T, Fn);
> - }
> - };
> -
> /// RegisterTargetMachine - Helper template for registering a target machine
> /// implementation, for use in the target machine initialization
> /// function. Usage:
> @@ -931,9 +858,10 @@
> }
>
> private:
> - static TargetAsmParser *Allocator(const Target &T, MCAsmParser &P,
> - TargetMachine &TM) {
> - return new AsmParserImpl(T, P, TM);
> + static TargetAsmParser *Allocator(const Target &T, StringRef TT,
> + StringRef CPU, StringRef FS,
> + MCAsmParser &P) {
> + return new AsmParserImpl(T, TT, CPU, FS, P);
> }
> };
>
>
> Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp?rev=134678&r1=134677&r2=134678&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp (original)
> +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp Thu Jul 7 20:53:10 2011
> @@ -111,7 +111,12 @@
> OwningPtr<MCAsmParser> Parser(createMCAsmParser(TM.getTarget(), SrcMgr,
> OutContext, OutStreamer,
> *MAI));
> - OwningPtr<TargetAsmParser> TAP(TM.getTarget().createAsmParser(*Parser, TM));
> +
> + OwningPtr<TargetAsmParser>
> + TAP(TM.getTarget().createAsmParser(TM.getTargetTriple(),
> + TM.getTargetCPU(),
> + TM.getTargetFeatureString(),
> + *Parser));
> if (!TAP)
> report_fatal_error("Inline asm not supported by this streamer because"
> " we don't have an asm parser for this target\n");
>
> Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original)
> +++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Thu Jul 7 20:53:10 2011
> @@ -98,10 +98,10 @@
> EnableFastISelOption("fast-isel", cl::Hidden,
> cl::desc("Enable the \"fast\" instruction selector"));
>
> -LLVMTargetMachine::LLVMTargetMachine(const Target &T,
> - const std::string &Triple)
> - : TargetMachine(T), TargetTriple(Triple) {
> - AsmInfo = T.createAsmInfo(TargetTriple);
> +LLVMTargetMachine::LLVMTargetMachine(const Target &T, StringRef Triple,
> + StringRef CPU, StringRef FS)
> + : TargetMachine(T, Triple, CPU, FS) {
> + AsmInfo = T.createAsmInfo(Triple);
> }
>
> // Set the default code model for the JIT for a generic target.
> @@ -143,7 +143,7 @@
> TargetAsmBackend *TAB = 0;
> if (ShowMCEncoding) {
> MCE = getTarget().createCodeEmitter(*this, *Context);
> - TAB = getTarget().createAsmBackend(TargetTriple);
> + TAB = getTarget().createAsmBackend(getTargetTriple());
> }
>
> MCStreamer *S = getTarget().createAsmStreamer(*Context, Out,
> @@ -160,12 +160,12 @@
> // Create the code emitter for the target if it exists. If not, .o file
> // emission fails.
> MCCodeEmitter *MCE = getTarget().createCodeEmitter(*this, *Context);
> - TargetAsmBackend *TAB = getTarget().createAsmBackend(TargetTriple);
> + TargetAsmBackend *TAB = getTarget().createAsmBackend(getTargetTriple());
> if (MCE == 0 || TAB == 0)
> return true;
>
> - AsmStreamer.reset(getTarget().createObjectStreamer(TargetTriple, *Context,
> - *TAB, Out, MCE,
> + AsmStreamer.reset(getTarget().createObjectStreamer(getTargetTriple(),
> + *Context, *TAB, Out, MCE,
> hasMCRelaxAll(),
> hasMCNoExecStack()));
> AsmStreamer.get()->InitSections();
> @@ -241,12 +241,12 @@
> // Create the code emitter for the target if it exists. If not, .o file
> // emission fails.
> MCCodeEmitter *MCE = getTarget().createCodeEmitter(*this, *Ctx);
> - TargetAsmBackend *TAB = getTarget().createAsmBackend(TargetTriple);
> + TargetAsmBackend *TAB = getTarget().createAsmBackend(getTargetTriple());
> if (MCE == 0 || TAB == 0)
> return true;
>
> OwningPtr<MCStreamer> AsmStreamer;
> - AsmStreamer.reset(getTarget().createObjectStreamer(TargetTriple, *Ctx,
> + AsmStreamer.reset(getTarget().createObjectStreamer(getTargetTriple(), *Ctx,
> *TAB, Out, MCE,
> hasMCRelaxAll(),
> hasMCNoExecStack()));
>
> Modified: llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp?rev=134678&r1=134677&r2=134678&view=diff
> ==============================================================================
> --- llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp (original)
> +++ llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp Thu Jul 7 20:53:10 2011
> @@ -171,7 +171,7 @@
> std::string featureString;
> TargetMachine.reset(Tgt->createTargetMachine(tripleString, CPU,
> featureString));
> -
> +
> const TargetRegisterInfo *registerInfo = TargetMachine->getRegisterInfo();
>
> if (!registerInfo)
> @@ -183,7 +183,7 @@
>
> if (!AsmInfo)
> return;
> -
> +
> Disassembler.reset(Tgt->createMCDisassembler());
>
> if (!Disassembler)
> @@ -371,8 +371,10 @@
> OwningPtr<MCAsmParser> genericParser(createMCAsmParser(*Tgt, sourceMgr,
> context, *streamer,
> *AsmInfo));
> - OwningPtr<TargetAsmParser> TargetParser(Tgt->createAsmParser(*genericParser,
> - *TargetMachine));
> +
> + StringRef triple = tripleFromArch(Key.Arch);
> + OwningPtr<TargetAsmParser> TargetParser(Tgt->createAsmParser(triple, "", "",
> + *genericParser));
>
> AsmToken OpcodeToken = genericParser->Lex();
> AsmToken NextToken = genericParser->Lex(); // consume next token, because specificParser expects us to
>
> Modified: llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.h?rev=134678&r1=134677&r2=134678&view=diff
> ==============================================================================
> --- llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.h (original)
> +++ llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.h Thu Jul 7 20:53:10 2011
> @@ -41,6 +41,7 @@
> class MCInst;
> class MCParsedAsmOperand;
> class MCStreamer;
> +class MCSubtargetInfo;
> template <typename T> class SmallVectorImpl;
> class SourceMgr;
> class Target;
>
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=134678&r1=134677&r2=134678&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Jul 7 20:53:10 2011
> @@ -147,35 +147,48 @@
> //===----------------------------------------------------------------------===//
> // ARM Instruction Predicate Definitions.
> //
> -def HasV4T : Predicate<"Subtarget->hasV4TOps()">, AssemblerPredicate;
> +def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
> + AssemblerPredicate<"HasV4TOps">;
> def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
> def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
> -def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, AssemblerPredicate;
> -def HasV6 : Predicate<"Subtarget->hasV6Ops()">, AssemblerPredicate;
> +def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
> + AssemblerPredicate<"HasV5TEOps">;
> +def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
> + AssemblerPredicate<"HasV6Ops">;
> def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
> -def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, AssemblerPredicate;
> +def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
> + AssemblerPredicate<"HasV6T2Ops">;
> def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
> -def HasV7 : Predicate<"Subtarget->hasV7Ops()">, AssemblerPredicate;
> +def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
> + AssemblerPredicate<"HasV7Ops">;
> def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
> -def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, AssemblerPredicate;
> -def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, AssemblerPredicate;
> -def HasNEON : Predicate<"Subtarget->hasNEON()">, AssemblerPredicate;
> -def HasFP16 : Predicate<"Subtarget->hasFP16()">, AssemblerPredicate;
> -def HasDivide : Predicate<"Subtarget->hasDivide()">, AssemblerPredicate;
> +def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
> + AssemblerPredicate<"FeatureVFP2">;
> +def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
> + AssemblerPredicate<"FeatureVFP3">;
> +def HasNEON : Predicate<"Subtarget->hasNEON()">,
> + AssemblerPredicate<"FeatureNEON">;
> +def HasFP16 : Predicate<"Subtarget->hasFP16()">,
> + AssemblerPredicate<"FeatureFP16">;
> +def HasDivide : Predicate<"Subtarget->hasDivide()">,
> + AssemblerPredicate<"FeatureHWDiv">;
> def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
> - AssemblerPredicate;
> + AssemblerPredicate<"FeatureT2XtPk">;
> def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
> - AssemblerPredicate;
> + AssemblerPredicate<"FeatureDSPThumb2">;
> def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
> - AssemblerPredicate;
> + AssemblerPredicate<"FeatureDB">;
> def HasMP : Predicate<"Subtarget->hasMPExtension()">,
> - AssemblerPredicate;
> + AssemblerPredicate<"FeatureMP">;
> def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
> def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
> -def IsThumb : Predicate<"Subtarget->isThumb()">, AssemblerPredicate;
> +def IsThumb : Predicate<"Subtarget->isThumb()">,
> + AssemblerPredicate<"ModeThumb">;
> def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
> -def IsThumb2 : Predicate<"Subtarget->isThumb2()">, AssemblerPredicate;
> -def IsARM : Predicate<"!Subtarget->isThumb()">, AssemblerPredicate;
> +def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
> + AssemblerPredicate<"ModeThumb,FeatureThumb2">;
> +def IsARM : Predicate<"!Subtarget->isThumb()">,
> + AssemblerPredicate<"!ModeThumb">;
> def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
> def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
>
>
> Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Thu Jul 7 20:53:10 2011
> @@ -18,9 +18,10 @@
> #include "llvm/Support/CommandLine.h"
> #include "llvm/ADT/SmallVector.h"
>
> -#define GET_SUBTARGETINFO_CTOR
> +#define GET_SUBTARGETINFO_ENUM
> #define GET_SUBTARGETINFO_MC_DESC
> #define GET_SUBTARGETINFO_TARGET_DESC
> +#define GET_SUBTARGETINFO_CTOR
> #include "ARMGenSubtargetInfo.inc"
>
> using namespace llvm;
>
> Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Thu Jul 7 20:53:10 2011
> @@ -80,7 +80,7 @@
> const std::string &TT,
> const std::string &CPU,
> const std::string &FS)
> - : LLVMTargetMachine(T, TT),
> + : LLVMTargetMachine(T, TT, CPU, FS),
> Subtarget(TT, CPU, FS),
> JITInfo(),
> InstrItins(Subtarget.getInstrItineraryData()) {
>
> Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=134678&r1=134677&r2=134678&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Thu Jul 7 20:53:10 2011
> @@ -20,6 +20,7 @@
> #include "llvm/MC/MCStreamer.h"
> #include "llvm/MC/MCExpr.h"
> #include "llvm/MC/MCInst.h"
> +#include "llvm/MC/MCSubtargetInfo.h"
> #include "llvm/Target/TargetRegistry.h"
> #include "llvm/Target/TargetAsmParser.h"
> #include "llvm/Support/SourceMgr.h"
> @@ -28,6 +29,10 @@
> #include "llvm/ADT/StringExtras.h"
> #include "llvm/ADT/StringSwitch.h"
> #include "llvm/ADT/Twine.h"
> +
> +#define GET_SUBTARGETINFO_ENUM
> +#include "ARMGenSubtargetInfo.inc"
> +
> using namespace llvm;
>
> namespace {
> @@ -36,7 +41,7 @@
>
> class ARMAsmParser : public TargetAsmParser {
> MCAsmParser &Parser;
> - TargetMachine &TM;
> + MCSubtargetInfo *STI;
>
> MCAsmParser &getParser() const { return Parser; }
> MCAsmLexer &getLexer() const { return Parser.getLexer(); }
> @@ -79,6 +84,15 @@
> void GetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
> bool &CanAcceptPredicationCode);
>
> + bool isThumb() const {
> + // FIXME: Can tablegen auto-generate this?
> + return (STI->getFeatureBits() & ARM::ModeThumb) != 0;
> + }
> +
> + bool isThumbOne() const {
> + return isThumb() && (STI->getFeatureBits() & ARM::FeatureThumb2) == 0;
> + }
> +
> /// @name Auto-generated Match Functions
> /// {
>
> @@ -113,13 +127,15 @@
> const SmallVectorImpl<MCParsedAsmOperand*> &);
>
> public:
> - ARMAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM)
> - : TargetAsmParser(T), Parser(_Parser), TM(_TM) {
> - MCAsmParserExtension::Initialize(_Parser);
> - // Initialize the set of available features.
> - setAvailableFeatures(ComputeAvailableFeatures(
> - &TM.getSubtarget<ARMSubtarget>()));
> - }
> + ARMAsmParser(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
> + MCAsmParser &_Parser)
> + : TargetAsmParser(T), Parser(_Parser) {
> + STI = ARM_MC::createARMMCSubtargetInfo(TT, CPU, FS);
> +
> + MCAsmParserExtension::Initialize(_Parser);
> + // Initialize the set of available features.
> + setAvailableFeatures(ComputeAvailableFeatures(STI->getFeatureBits()));
> + }
>
> virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
> SmallVectorImpl<MCParsedAsmOperand*> &Operands);
> @@ -1852,9 +1868,6 @@
> void ARMAsmParser::
> GetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
> bool &CanAcceptPredicationCode) {
> - bool isThumbOne = TM.getSubtarget<ARMSubtarget>().isThumb1Only();
> - bool isThumb = TM.getSubtarget<ARMSubtarget>().isThumb();
> -
> if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
> Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
> Mnemonic == "smull" || Mnemonic == "add" || Mnemonic == "adc" ||
> @@ -1863,7 +1876,7 @@
> Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
> Mnemonic == "sbc" || Mnemonic == "mla" || Mnemonic == "umull" ||
> Mnemonic == "eor" || Mnemonic == "smlal" ||
> - (Mnemonic == "mov" && !isThumbOne)) {
> + (Mnemonic == "mov" && !isThumbOne())) {
> CanAcceptCarrySet = true;
> } else {
> CanAcceptCarrySet = false;
> @@ -1880,7 +1893,7 @@
> CanAcceptPredicationCode = true;
> }
>
> - if (isThumb)
> + if (isThumb())
> if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
> Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
> CanAcceptPredicationCode = false;
> @@ -2207,12 +2220,12 @@
> // includes Feature_IsThumb or not to match the right instructions. This is
> // blocked on the FIXME in llvm-mc.cpp when creating the TargetMachine.
> if (Val == 16){
> - assert(TM.getSubtarget<ARMSubtarget>().isThumb() &&
> + assert(isThumb() &&
> "switching between arm/thumb not yet suppported via .code 16)");
> getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
> }
> else{
> - assert(!TM.getSubtarget<ARMSubtarget>().isThumb() &&
> + assert(!isThumb() &&
> "switching between thumb/arm not yet suppported via .code 32)");
> getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
> }
>
> Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp?rev=134678&r1=134677&r2=134678&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp Thu Jul 7 20:53:10 2011
> @@ -23,65 +23,12 @@
> #define GET_INSTRINFO_MC_DESC
> #include "ARMGenInstrInfo.inc"
>
> +#define GET_SUBTARGETINFO_ENUM
> #define GET_SUBTARGETINFO_MC_DESC
> #include "ARMGenSubtargetInfo.inc"
>
> using namespace llvm;
>
> -MCInstrInfo *createARMMCInstrInfo() {
> - MCInstrInfo *X = new MCInstrInfo();
> - InitARMMCInstrInfo(X);
> - return X;
> -}
> -
> -MCRegisterInfo *createARMMCRegisterInfo() {
> - MCRegisterInfo *X = new MCRegisterInfo();
> - InitARMMCRegisterInfo(X);
> - return X;
> -}
> -
> -MCSubtargetInfo *createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
> - StringRef FS) {
> - std::string ArchFS = ARM_MC::ParseARMTriple(TT);
> - if (!FS.empty()) {
> - if (!ArchFS.empty())
> - ArchFS = ArchFS + "," + FS.str();
> - else
> - ArchFS = FS;
> - }
> -
> - MCSubtargetInfo *X = new MCSubtargetInfo();
> - InitARMMCSubtargetInfo(X, CPU, ArchFS);
> - return X;
> -}
> -
> -// Force static initialization.
> -extern "C" void LLVMInitializeARMMCInstrInfo() {
> - RegisterMCInstrInfo<MCInstrInfo> X(TheARMTarget);
> - RegisterMCInstrInfo<MCInstrInfo> Y(TheThumbTarget);
> -
> - TargetRegistry::RegisterMCInstrInfo(TheARMTarget, createARMMCInstrInfo);
> - TargetRegistry::RegisterMCInstrInfo(TheThumbTarget, createARMMCInstrInfo);
> -}
> -
> -extern "C" void LLVMInitializeARMMCRegInfo() {
> - RegisterMCRegInfo<MCRegisterInfo> X(TheARMTarget);
> - RegisterMCRegInfo<MCRegisterInfo> Y(TheThumbTarget);
> -
> - TargetRegistry::RegisterMCRegInfo(TheARMTarget, createARMMCRegisterInfo);
> - TargetRegistry::RegisterMCRegInfo(TheThumbTarget, createARMMCRegisterInfo);
> -}
> -
> -extern "C" void LLVMInitializeARMMCSubtargetInfo() {
> - RegisterMCSubtargetInfo<MCSubtargetInfo> X(TheARMTarget);
> - RegisterMCSubtargetInfo<MCSubtargetInfo> Y(TheThumbTarget);
> -
> - TargetRegistry::RegisterMCSubtargetInfo(TheARMTarget,
> - createARMMCSubtargetInfo);
> - TargetRegistry::RegisterMCSubtargetInfo(TheThumbTarget,
> - createARMMCSubtargetInfo);
> -}
> -
> std::string ARM_MC::ParseARMTriple(StringRef TT) {
> // Set the boolean corresponding to the current target triple, or the default
> // if one cannot be determined, to true.
> @@ -135,3 +82,47 @@
>
> return ARMArchFeature;
> }
> +
> +MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
> + StringRef FS) {
> + std::string ArchFS = ARM_MC::ParseARMTriple(TT);
> + if (!FS.empty()) {
> + if (!ArchFS.empty())
> + ArchFS = ArchFS + "," + FS.str();
> + else
> + ArchFS = FS;
> + }
> +
> + MCSubtargetInfo *X = new MCSubtargetInfo();
> + InitARMMCSubtargetInfo(X, CPU, ArchFS);
> + return X;
> +}
> +
> +MCInstrInfo *createARMMCInstrInfo() {
> + MCInstrInfo *X = new MCInstrInfo();
> + InitARMMCInstrInfo(X);
> + return X;
> +}
> +
> +MCRegisterInfo *createARMMCRegisterInfo() {
> + MCRegisterInfo *X = new MCRegisterInfo();
> + InitARMMCRegisterInfo(X);
> + return X;
> +}
> +
> +// Force static initialization.
> +extern "C" void LLVMInitializeARMMCInstrInfo() {
> + RegisterMCInstrInfo<MCInstrInfo> X(TheARMTarget);
> + RegisterMCInstrInfo<MCInstrInfo> Y(TheThumbTarget);
> +
> + TargetRegistry::RegisterMCInstrInfo(TheARMTarget, createARMMCInstrInfo);
> + TargetRegistry::RegisterMCInstrInfo(TheThumbTarget, createARMMCInstrInfo);
> +}
> +
> +extern "C" void LLVMInitializeARMMCRegInfo() {
> + RegisterMCRegInfo<MCRegisterInfo> X(TheARMTarget);
> + RegisterMCRegInfo<MCRegisterInfo> Y(TheThumbTarget);
> +
> + TargetRegistry::RegisterMCRegInfo(TheARMTarget, createARMMCRegisterInfo);
> + TargetRegistry::RegisterMCRegInfo(TheThumbTarget, createARMMCRegisterInfo);
> +}
>
> Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h?rev=134678&r1=134677&r2=134678&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h (original)
> +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h Thu Jul 7 20:53:10 2011
> @@ -17,6 +17,7 @@
> #include <string>
>
> namespace llvm {
> +class MCSubtargetInfo;
> class Target;
> class StringRef;
>
> @@ -24,6 +25,12 @@
>
> namespace ARM_MC {
> std::string ParseARMTriple(StringRef TT);
> +
> + /// createARMMCSubtargetInfo - Create a ARM MCSubtargetInfo instance.
> + /// This is exposed so Asm parser, etc. do not need to go through
> + /// TargetRegistry.
> + MCSubtargetInfo *createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
> + StringRef FS);
> }
>
> } // End llvm namespace
>
> Modified: llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp (original)
> +++ llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp Thu Jul 7 20:53:10 2011
> @@ -14,9 +14,10 @@
> #include "AlphaSubtarget.h"
> #include "Alpha.h"
>
> -#define GET_SUBTARGETINFO_CTOR
> +#define GET_SUBTARGETINFO_ENUM
> #define GET_SUBTARGETINFO_MC_DESC
> #define GET_SUBTARGETINFO_TARGET_DESC
> +#define GET_SUBTARGETINFO_CTOR
> #include "AlphaGenSubtargetInfo.inc"
>
> using namespace llvm;
>
> Modified: llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp Thu Jul 7 20:53:10 2011
> @@ -27,7 +27,7 @@
> AlphaTargetMachine::AlphaTargetMachine(const Target &T, const std::string &TT,
> const std::string &CPU,
> const std::string &FS)
> - : LLVMTargetMachine(T, TT),
> + : LLVMTargetMachine(T, TT, CPU, FS),
> DataLayout("e-f128:128:128-n64"),
> FrameLowering(Subtarget),
> Subtarget(TT, CPU, FS),
>
> Modified: llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp (original)
> +++ llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp Thu Jul 7 20:53:10 2011
> @@ -13,9 +13,10 @@
>
> #include "BlackfinSubtarget.h"
>
> -#define GET_SUBTARGETINFO_CTOR
> +#define GET_SUBTARGETINFO_ENUM
> #define GET_SUBTARGETINFO_MC_DESC
> #define GET_SUBTARGETINFO_TARGET_DESC
> +#define GET_SUBTARGETINFO_CTOR
> #include "BlackfinGenSubtargetInfo.inc"
>
> using namespace llvm;
>
> Modified: llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp Thu Jul 7 20:53:10 2011
> @@ -28,7 +28,7 @@
> const std::string &TT,
> const std::string &CPU,
> const std::string &FS)
> - : LLVMTargetMachine(T, TT),
> + : LLVMTargetMachine(T, TT, CPU, FS),
> DataLayout("e-p:32:32-i64:32-f64:32-n32"),
> Subtarget(TT, CPU, FS),
> TLInfo(*this),
>
> Modified: llvm/trunk/lib/Target/CBackend/CTargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CTargetMachine.h?rev=134678&r1=134677&r2=134678&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/CBackend/CTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/CBackend/CTargetMachine.h Thu Jul 7 20:53:10 2011
> @@ -22,7 +22,7 @@
> struct CTargetMachine : public TargetMachine {
> CTargetMachine(const Target &T, const std::string &TT,
> const std::string &CPU, const std::string &FS)
> - : TargetMachine(T) {}
> + : TargetMachine(T, TT, CPU, FS) {}
>
> virtual bool addPassesToEmitFile(PassManagerBase &PM,
> formatted_raw_ostream &Out,
>
> Modified: llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp (original)
> +++ llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp Thu Jul 7 20:53:10 2011
> @@ -13,12 +13,13 @@
>
> #include "SPUSubtarget.h"
> #include "SPU.h"
> -#include "llvm/ADT/SmallVector.h"
> #include "SPURegisterInfo.h"
> +#include "llvm/ADT/SmallVector.h"
>
> -#define GET_SUBTARGETINFO_CTOR
> +#define GET_SUBTARGETINFO_ENUM
> #define GET_SUBTARGETINFO_MC_DESC
> #define GET_SUBTARGETINFO_TARGET_DESC
> +#define GET_SUBTARGETINFO_CTOR
> #include "SPUGenSubtargetInfo.inc"
>
> using namespace llvm;
>
> Modified: llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp Thu Jul 7 20:53:10 2011
> @@ -36,7 +36,7 @@
>
> SPUTargetMachine::SPUTargetMachine(const Target &T, const std::string &TT,
> const std::string &CPU,const std::string &FS)
> - : LLVMTargetMachine(T, TT),
> + : LLVMTargetMachine(T, TT, CPU, FS),
> Subtarget(TT, CPU, FS),
> DataLayout(Subtarget.getTargetDataString()),
> InstrInfo(*this),
>
> Modified: llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h?rev=134678&r1=134677&r2=134678&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h (original)
> +++ llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h Thu Jul 7 20:53:10 2011
> @@ -24,7 +24,7 @@
> struct CPPTargetMachine : public TargetMachine {
> CPPTargetMachine(const Target &T, const std::string &TT,
> const std::string &CPU, const std::string &FS)
> - : TargetMachine(T) {}
> + : TargetMachine(T, TT, CPU, FS) {}
>
> virtual bool addPassesToEmitFile(PassManagerBase &PM,
> formatted_raw_ostream &Out,
>
> Modified: llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp?rev=134678&r1=134677&r2=134678&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp (original)
> +++ llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp Thu Jul 7 20:53:10 2011
> @@ -32,7 +32,6 @@
>
> class MBlazeAsmParser : public TargetAsmParser {
> MCAsmParser &Parser;
> - TargetMachine &TM;
>
> MCAsmParser &getParser() const { return Parser; }
> MCAsmLexer &getLexer() const { return Parser.getLexer(); }
> @@ -64,8 +63,9 @@
>
>
> public:
> - MBlazeAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM)
> - : TargetAsmParser(T), Parser(_Parser), TM(_TM) {}
> + MBlazeAsmParser(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
> + MCAsmParser &_Parser)
> + : TargetAsmParser(T), Parser(_Parser) {}
>
> virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
> SmallVectorImpl<MCParsedAsmOperand*> &Operands);
>
> Modified: llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp (original)
> +++ llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp Thu Jul 7 20:53:10 2011
> @@ -16,9 +16,10 @@
> #include "MBlazeRegisterInfo.h"
> #include "llvm/Support/CommandLine.h"
>
> -#define GET_SUBTARGETINFO_CTOR
> +#define GET_SUBTARGETINFO_ENUM
> #define GET_SUBTARGETINFO_MC_DESC
> #define GET_SUBTARGETINFO_TARGET_DESC
> +#define GET_SUBTARGETINFO_CTOR
> #include "MBlazeGenSubtargetInfo.inc"
>
> using namespace llvm;
> @@ -61,4 +62,3 @@
> CriticalPathRCs.push_back(&MBlaze::GPRRegClass);
> return HasItin && OptLevel >= CodeGenOpt::Default;
> }
> -
>
> Modified: llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp Thu Jul 7 20:53:10 2011
> @@ -81,7 +81,7 @@
> MBlazeTargetMachine::
> MBlazeTargetMachine(const Target &T, const std::string &TT,
> const std::string &CPU, const std::string &FS):
> - LLVMTargetMachine(T, TT),
> + LLVMTargetMachine(T, TT, CPU, FS),
> Subtarget(TT, CPU, FS),
> DataLayout("E-p:32:32:32-i8:8:8-i16:16:16"),
> InstrInfo(*this),
>
> Modified: llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp (original)
> +++ llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp Thu Jul 7 20:53:10 2011
> @@ -14,9 +14,10 @@
> #include "MSP430Subtarget.h"
> #include "MSP430.h"
>
> -#define GET_SUBTARGETINFO_CTOR
> +#define GET_SUBTARGETINFO_ENUM
> #define GET_SUBTARGETINFO_MC_DESC
> #define GET_SUBTARGETINFO_TARGET_DESC
> +#define GET_SUBTARGETINFO_CTOR
> #include "MSP430GenSubtargetInfo.inc"
>
> using namespace llvm;
>
> Modified: llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp Thu Jul 7 20:53:10 2011
> @@ -30,7 +30,7 @@
> const std::string &TT,
> const std::string &CPU,
> const std::string &FS)
> - : LLVMTargetMachine(T, TT),
> + : LLVMTargetMachine(T, TT, CPU, FS),
> Subtarget(TT, CPU, FS),
> // FIXME: Check TargetData string.
> DataLayout("e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"),
>
> Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp Thu Jul 7 20:53:10 2011
> @@ -14,9 +14,10 @@
> #include "MipsSubtarget.h"
> #include "Mips.h"
>
> -#define GET_SUBTARGETINFO_CTOR
> +#define GET_SUBTARGETINFO_ENUM
> #define GET_SUBTARGETINFO_MC_DESC
> #define GET_SUBTARGETINFO_TARGET_DESC
> +#define GET_SUBTARGETINFO_CTOR
> #include "MipsGenSubtargetInfo.inc"
>
> using namespace llvm;
>
> Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp Thu Jul 7 20:53:10 2011
> @@ -37,7 +37,7 @@
> MipsTargetMachine(const Target &T, const std::string &TT,
> const std::string &CPU, const std::string &FS,
> bool isLittle=false):
> - LLVMTargetMachine(T, TT),
> + LLVMTargetMachine(T, TT, CPU, FS),
> Subtarget(TT, CPU, FS, isLittle),
> DataLayout(isLittle ?
> std::string("e-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32") :
>
> Modified: llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp (original)
> +++ llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp Thu Jul 7 20:53:10 2011
> @@ -14,9 +14,10 @@
> #include "PTXSubtarget.h"
> #include "llvm/Support/ErrorHandling.h"
>
> -#define GET_SUBTARGETINFO_CTOR
> +#define GET_SUBTARGETINFO_ENUM
> #define GET_SUBTARGETINFO_MC_DESC
> #define GET_SUBTARGETINFO_TARGET_DESC
> +#define GET_SUBTARGETINFO_CTOR
> #include "PTXGenSubtargetInfo.inc"
>
> using namespace llvm;
>
> Modified: llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp Thu Jul 7 20:53:10 2011
> @@ -55,7 +55,7 @@
> const std::string &CPU,
> const std::string &FS,
> bool is64Bit)
> - : LLVMTargetMachine(T, TT),
> + : LLVMTargetMachine(T, TT, CPU, FS),
> DataLayout(is64Bit ? DataLayout64 : DataLayout32),
> Subtarget(TT, CPU, FS, is64Bit),
> FrameLowering(Subtarget),
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp Thu Jul 7 20:53:10 2011
> @@ -17,9 +17,10 @@
> #include "llvm/Target/TargetMachine.h"
> #include <cstdlib>
>
> -#define GET_SUBTARGETINFO_CTOR
> +#define GET_SUBTARGETINFO_ENUM
> #define GET_SUBTARGETINFO_MC_DESC
> #define GET_SUBTARGETINFO_TARGET_DESC
> +#define GET_SUBTARGETINFO_CTOR
> #include "PPCGenSubtargetInfo.inc"
>
> using namespace llvm;
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp Thu Jul 7 20:53:10 2011
> @@ -69,7 +69,7 @@
> PPCTargetMachine::PPCTargetMachine(const Target &T, const std::string &TT,
> const std::string &CPU,
> const std::string &FS, bool is64Bit)
> - : LLVMTargetMachine(T, TT),
> + : LLVMTargetMachine(T, TT, CPU, FS),
> Subtarget(TT, CPU, FS, is64Bit),
> DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this),
> FrameLowering(Subtarget), JITInfo(*this, is64Bit),
>
> Modified: llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp (original)
> +++ llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp Thu Jul 7 20:53:10 2011
> @@ -13,9 +13,10 @@
>
> #include "SparcSubtarget.h"
>
> -#define GET_SUBTARGETINFO_CTOR
> +#define GET_SUBTARGETINFO_ENUM
> #define GET_SUBTARGETINFO_MC_DESC
> #define GET_SUBTARGETINFO_TARGET_DESC
> +#define GET_SUBTARGETINFO_CTOR
> #include "SparcGenSubtargetInfo.inc"
>
> using namespace llvm;
>
> Modified: llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp Thu Jul 7 20:53:10 2011
> @@ -32,7 +32,7 @@
> SparcTargetMachine::SparcTargetMachine(const Target &T, const std::string &TT,
> const std::string &CPU,
> const std::string &FS, bool is64bit)
> - : LLVMTargetMachine(T, TT),
> + : LLVMTargetMachine(T, TT, CPU, FS),
> Subtarget(TT, CPU, FS, is64bit),
> DataLayout(Subtarget.getDataLayout()),
> TLInfo(*this), TSInfo(*this), InstrInfo(Subtarget),
>
> Modified: llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp (original)
> +++ llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp Thu Jul 7 20:53:10 2011
> @@ -16,9 +16,10 @@
> #include "llvm/GlobalValue.h"
> #include "llvm/Target/TargetMachine.h"
>
> -#define GET_SUBTARGETINFO_CTOR
> +#define GET_SUBTARGETINFO_ENUM
> #define GET_SUBTARGETINFO_MC_DESC
> #define GET_SUBTARGETINFO_TARGET_DESC
> +#define GET_SUBTARGETINFO_CTOR
> #include "SystemZGenSubtargetInfo.inc"
>
> using namespace llvm;
>
> Modified: llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp Thu Jul 7 20:53:10 2011
> @@ -26,7 +26,7 @@
> const std::string &TT,
> const std::string &CPU,
> const std::string &FS)
> - : LLVMTargetMachine(T, TT),
> + : LLVMTargetMachine(T, TT, CPU, FS),
> Subtarget(TT, CPU, FS),
> DataLayout("E-p:64:64:64-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:32"
> "-f64:64:64-f128:128:128-a0:16:16-n32:64"),
>
> Modified: llvm/trunk/lib/Target/TargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/TargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/TargetMachine.cpp Thu Jul 7 20:53:10 2011
> @@ -216,8 +216,9 @@
> // TargetMachine Class
> //
>
> -TargetMachine::TargetMachine(const Target &T)
> - : TheTarget(T), AsmInfo(0),
> +TargetMachine::TargetMachine(const Target &T,
> + StringRef TT, StringRef CPU, StringRef FS)
> + : TheTarget(T), TargetTriple(TT), TargetCPU(CPU), TargetFS(FS), AsmInfo(0),
> MCRelaxAll(false),
> MCNoExecStack(false),
> MCSaveTempLabels(false),
>
> Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=134678&r1=134677&r2=134678&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original)
> +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Thu Jul 7 20:53:10 2011
> @@ -15,6 +15,7 @@
> #include "llvm/MC/MCStreamer.h"
> #include "llvm/MC/MCExpr.h"
> #include "llvm/MC/MCInst.h"
> +#include "llvm/MC/MCSubtargetInfo.h"
> #include "llvm/MC/MCParser/MCAsmLexer.h"
> #include "llvm/MC/MCParser/MCAsmParser.h"
> #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
> @@ -25,6 +26,10 @@
> #include "llvm/ADT/Twine.h"
> #include "llvm/Support/SourceMgr.h"
> #include "llvm/Support/raw_ostream.h"
> +
> +#define GET_SUBTARGETINFO_ENUM
> +#include "X86GenSubtargetInfo.inc"
> +
> using namespace llvm;
>
> namespace {
> @@ -32,10 +37,7 @@
>
> class X86ATTAsmParser : public TargetAsmParser {
> MCAsmParser &Parser;
> - TargetMachine &TM;
> -
> -protected:
> - unsigned Is64Bit : 1;
> + MCSubtargetInfo *STI;
>
> private:
> MCAsmParser &getParser() const { return Parser; }
> @@ -61,6 +63,11 @@
> /// or %es:(%edi) in 32bit mode.
> bool isDstOp(X86Operand &Op);
>
> + bool is64Bit() {
> + // FIXME: Can tablegen auto-generate this?
> + return (STI->getFeatureBits() & X86::Mode64Bit) != 0;
> + }
> +
> /// @name Auto-generated Matcher Functions
> /// {
>
> @@ -70,12 +77,13 @@
> /// }
>
> public:
> - X86ATTAsmParser(const Target &T, MCAsmParser &parser, TargetMachine &TM)
> - : TargetAsmParser(T), Parser(parser), TM(TM) {
> + X86ATTAsmParser(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
> + MCAsmParser &parser)
> + : TargetAsmParser(T), Parser(parser) {
> + STI = X86_MC::createX86MCSubtargetInfo(TT, CPU, FS);
>
> // Initialize the set of available features.
> - setAvailableFeatures(ComputeAvailableFeatures(
> - &TM.getSubtarget<X86Subtarget>()));
> + setAvailableFeatures(ComputeAvailableFeatures(STI->getFeatureBits()));
> }
> virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
>
> @@ -84,23 +92,6 @@
>
> virtual bool ParseDirective(AsmToken DirectiveID);
> };
> -
> -class X86_32ATTAsmParser : public X86ATTAsmParser {
> -public:
> - X86_32ATTAsmParser(const Target &T, MCAsmParser &Parser, TargetMachine &TM)
> - : X86ATTAsmParser(T, Parser, TM) {
> - Is64Bit = false;
> - }
> -};
> -
> -class X86_64ATTAsmParser : public X86ATTAsmParser {
> -public:
> - X86_64ATTAsmParser(const Target &T, MCAsmParser &Parser, TargetMachine &TM)
> - : X86ATTAsmParser(T, Parser, TM) {
> - Is64Bit = true;
> - }
> -};
> -
> } // end anonymous namespace
>
> /// @name Auto-generated Match Functions
> @@ -365,7 +356,7 @@
> } // end anonymous namespace.
>
> bool X86ATTAsmParser::isSrcOp(X86Operand &Op) {
> - unsigned basereg = Is64Bit ? X86::RSI : X86::ESI;
> + unsigned basereg = is64Bit() ? X86::RSI : X86::ESI;
>
> return (Op.isMem() &&
> (Op.Mem.SegReg == 0 || Op.Mem.SegReg == X86::DS) &&
> @@ -375,7 +366,7 @@
> }
>
> bool X86ATTAsmParser::isDstOp(X86Operand &Op) {
> - unsigned basereg = Is64Bit ? X86::RDI : X86::EDI;
> + unsigned basereg = is64Bit() ? X86::RDI : X86::EDI;
>
> return Op.isMem() && Op.Mem.SegReg == X86::ES &&
> isa<MCConstantExpr>(Op.Mem.Disp) &&
> @@ -406,7 +397,7 @@
> // FIXME: This should be done using Requires<In32BitMode> and
> // Requires<In64BitMode> so "eiz" usage in 64-bit instructions
> // can be also checked.
> - if (RegNo == X86::RIZ && !Is64Bit)
> + if (RegNo == X86::RIZ && !is64Bit())
> return Error(Tok.getLoc(), "riz register in 64-bit mode only");
>
> // Parse "%st" as "%st(0)" and "%st(1)", which is multiple tokens.
> @@ -826,7 +817,7 @@
> // Transform "movs[bwl] %ds:(%esi), %es:(%edi)" into "movs[bwl]"
> if (Name.startswith("movs") && Operands.size() == 3 &&
> (Name == "movsb" || Name == "movsw" || Name == "movsl" ||
> - (Is64Bit && Name == "movsq"))) {
> + (is64Bit() && Name == "movsq"))) {
> X86Operand &Op = *(X86Operand*)Operands.begin()[1];
> X86Operand &Op2 = *(X86Operand*)Operands.begin()[2];
> if (isSrcOp(Op) && isDstOp(Op2)) {
> @@ -839,7 +830,7 @@
> // Transform "lods[bwl] %ds:(%esi),{%al,%ax,%eax,%rax}" into "lods[bwl]"
> if (Name.startswith("lods") && Operands.size() == 3 &&
> (Name == "lods" || Name == "lodsb" || Name == "lodsw" ||
> - Name == "lodsl" || (Is64Bit && Name == "lodsq"))) {
> + Name == "lodsl" || (is64Bit() && Name == "lodsq"))) {
> X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
> X86Operand *Op2 = static_cast<X86Operand*>(Operands[2]);
> if (isSrcOp(*Op1) && Op2->isReg()) {
> @@ -869,7 +860,7 @@
> // Transform "stos[bwl] {%al,%ax,%eax,%rax},%es:(%edi)" into "stos[bwl]"
> if (Name.startswith("stos") && Operands.size() == 3 &&
> (Name == "stos" || Name == "stosb" || Name == "stosw" ||
> - Name == "stosl" || (Is64Bit && Name == "stosq"))) {
> + Name == "stosl" || (is64Bit() && Name == "stosq"))) {
> X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
> X86Operand *Op2 = static_cast<X86Operand*>(Operands[2]);
> if (isDstOp(*Op2) && Op1->isReg()) {
> @@ -1144,8 +1135,8 @@
>
> // Force static initialization.
> extern "C" void LLVMInitializeX86AsmParser() {
> - RegisterAsmParser<X86_32ATTAsmParser> X(TheX86_32Target);
> - RegisterAsmParser<X86_64ATTAsmParser> Y(TheX86_64Target);
> + RegisterAsmParser<X86ATTAsmParser> X(TheX86_32Target);
> + RegisterAsmParser<X86ATTAsmParser> Y(TheX86_64Target);
> LLVMInitializeX86AsmLexer();
> }
>
>
> Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp?rev=134678&r1=134677&r2=134678&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp (original)
> +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp Thu Jul 7 20:53:10 2011
> @@ -25,6 +25,7 @@
> #define GET_INSTRINFO_MC_DESC
> #include "X86GenInstrInfo.inc"
>
> +#define GET_SUBTARGETINFO_ENUM
> #define GET_SUBTARGETINFO_MC_DESC
> #include "X86GenSubtargetInfo.inc"
>
> @@ -35,7 +36,7 @@
> Triple TheTriple(TT);
> if (TheTriple.getArch() == Triple::x86_64)
> return "+64bit-mode";
> - return "";
> + return "-64bit-mode";
> }
>
> /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
> @@ -128,20 +129,8 @@
> return false;
> }
>
> -MCInstrInfo *createX86MCInstrInfo() {
> - MCInstrInfo *X = new MCInstrInfo();
> - InitX86MCInstrInfo(X);
> - return X;
> -}
> -
> -MCRegisterInfo *createX86MCRegisterInfo() {
> - MCRegisterInfo *X = new MCRegisterInfo();
> - InitX86MCRegisterInfo(X);
> - return X;
> -}
> -
> -MCSubtargetInfo *createX86MCSubtargetInfo(StringRef TT, StringRef CPU,
> - StringRef FS) {
> +MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(StringRef TT, StringRef CPU,
> + StringRef FS) {
> std::string ArchFS = X86_MC::ParseX86Triple(TT);
> if (!FS.empty()) {
> if (!ArchFS.empty())
> @@ -159,7 +148,19 @@
> ArchFS = "+64bit-mode";
>
> MCSubtargetInfo *X = new MCSubtargetInfo();
> - InitX86MCSubtargetInfo(X, CPU, ArchFS);
> + InitX86MCSubtargetInfo(X, CPUName, ArchFS);
> + return X;
> +}
> +
> +MCInstrInfo *createX86MCInstrInfo() {
> + MCInstrInfo *X = new MCInstrInfo();
> + InitX86MCInstrInfo(X);
> + return X;
> +}
> +
> +MCRegisterInfo *createX86MCRegisterInfo() {
> + MCRegisterInfo *X = new MCRegisterInfo();
> + InitX86MCRegisterInfo(X);
> return X;
> }
>
> @@ -179,13 +180,3 @@
> TargetRegistry::RegisterMCRegInfo(TheX86_32Target, createX86MCRegisterInfo);
> TargetRegistry::RegisterMCRegInfo(TheX86_64Target, createX86MCRegisterInfo);
> }
> -
> -extern "C" void LLVMInitializeX86MCSubtargetInfo() {
> - RegisterMCSubtargetInfo<MCSubtargetInfo> X(TheX86_32Target);
> - RegisterMCSubtargetInfo<MCSubtargetInfo> Y(TheX86_64Target);
> -
> - TargetRegistry::RegisterMCSubtargetInfo(TheX86_32Target,
> - createX86MCSubtargetInfo);
> - TargetRegistry::RegisterMCSubtargetInfo(TheX86_64Target,
> - createX86MCSubtargetInfo);
> -}
>
> Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h?rev=134678&r1=134677&r2=134678&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h (original)
> +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h Thu Jul 7 20:53:10 2011
> @@ -17,6 +17,7 @@
> #include <string>
>
> namespace llvm {
> +class MCSubtargetInfo;
> class Target;
> class StringRef;
>
> @@ -31,9 +32,17 @@
> unsigned *rEBX, unsigned *rECX, unsigned *rEDX);
>
> void DetectFamilyModel(unsigned EAX, unsigned &Family, unsigned &Model);
> +
> + /// createARMMCSubtargetInfo - Create a X86 MCSubtargetInfo instance.
> + /// This is exposed so Asm parser, etc. do not need to go through
> + /// TargetRegistry.
> + MCSubtargetInfo *createX86MCSubtargetInfo(StringRef TT, StringRef CPU,
> + StringRef FS);
> }
> +
> } // End llvm namespace
>
> +
> // Defines symbolic names for X86 registers. This defines a mapping from
> // register name to register number.
> //
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=134678&r1=134677&r2=134678&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Thu Jul 7 20:53:10 2011
> @@ -438,8 +438,10 @@
> def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
> def FPStackf32 : Predicate<"!Subtarget->hasXMM()">;
> def FPStackf64 : Predicate<"!Subtarget->hasXMMInt()">;
> -def In32BitMode : Predicate<"!Subtarget->is64Bit()">, AssemblerPredicate;
> -def In64BitMode : Predicate<"Subtarget->is64Bit()">, AssemblerPredicate;
> +def In32BitMode : Predicate<"!Subtarget->is64Bit()">,
> + AssemblerPredicate<"!Mode64Bit">;
> +def In64BitMode : Predicate<"Subtarget->is64Bit()">,
> + AssemblerPredicate<"Mode64Bit">;
> def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
> def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
> def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
>
> Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Thu Jul 7 20:53:10 2011
> @@ -21,9 +21,10 @@
> #include "llvm/Target/TargetMachine.h"
> #include "llvm/ADT/SmallVector.h"
>
> -#define GET_SUBTARGETINFO_CTOR
> +#define GET_SUBTARGETINFO_ENUM
> #define GET_SUBTARGETINFO_MC_DESC
> #define GET_SUBTARGETINFO_TARGET_DESC
> +#define GET_SUBTARGETINFO_CTOR
> #include "X86GenSubtargetInfo.inc"
>
> using namespace llvm;
>
> Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Thu Jul 7 20:53:10 2011
> @@ -119,7 +119,7 @@
> X86TargetMachine::X86TargetMachine(const Target &T, const std::string &TT,
> const std::string &CPU,
> const std::string &FS, bool is64Bit)
> - : LLVMTargetMachine(T, TT),
> + : LLVMTargetMachine(T, TT, CPU, FS),
> Subtarget(TT, CPU, FS, StackAlignmentOverride),
> FrameLowering(*this, Subtarget),
> ELFWriterInfo(is64Bit, true) {
>
> Modified: llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp (original)
> +++ llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp Thu Jul 7 20:53:10 2011
> @@ -14,9 +14,10 @@
> #include "XCoreSubtarget.h"
> #include "XCore.h"
>
> -#define GET_SUBTARGETINFO_CTOR
> +#define GET_SUBTARGETINFO_ENUM
> #define GET_SUBTARGETINFO_MC_DESC
> #define GET_SUBTARGETINFO_TARGET_DESC
> +#define GET_SUBTARGETINFO_CTOR
> #include "XCoreGenSubtargetInfo.inc"
>
> using namespace llvm;
>
> Modified: llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp Thu Jul 7 20:53:10 2011
> @@ -23,7 +23,7 @@
> XCoreTargetMachine::XCoreTargetMachine(const Target &T, const std::string &TT,
> const std::string &CPU,
> const std::string &FS)
> - : LLVMTargetMachine(T, TT),
> + : LLVMTargetMachine(T, TT, CPU, FS),
> Subtarget(TT, CPU, FS),
> DataLayout("e-p:32:32:32-a0:0:32-f32:32:32-f64:32:32-i1:8:32-i8:8:32-"
> "i16:16:32-i32:32:32-i64:32:32-n32"),
>
> Modified: llvm/trunk/tools/llvm-mc/llvm-mc.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/llvm-mc.cpp?rev=134678&r1=134677&r2=134678&view=diff
> ==============================================================================
> --- llvm/trunk/tools/llvm-mc/llvm-mc.cpp (original)
> +++ llvm/trunk/tools/llvm-mc/llvm-mc.cpp Thu Jul 7 20:53:10 2011
> @@ -371,7 +371,8 @@
>
> OwningPtr<MCAsmParser> Parser(createMCAsmParser(*TheTarget, SrcMgr, Ctx,
> *Str.get(), *MAI));
> - OwningPtr<TargetAsmParser> TAP(TheTarget->createAsmParser(*Parser, *TM));
> + OwningPtr<TargetAsmParser>
> + TAP(TheTarget->createAsmParser(TripleName, MCPU, FeaturesStr, *Parser));
> if (!TAP) {
> errs() << ProgName
> << ": error: this target does not support assembly parsing.\n";
>
> Modified: llvm/trunk/tools/lto/LTOModule.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOModule.cpp?rev=134678&r1=134677&r2=134678&view=diff
> ==============================================================================
> --- llvm/trunk/tools/lto/LTOModule.cpp (original)
> +++ llvm/trunk/tools/lto/LTOModule.cpp Thu Jul 7 20:53:10 2011
> @@ -619,7 +619,10 @@
> Context, *Streamer,
> *_target->getMCAsmInfo()));
> OwningPtr<TargetAsmParser>
> - TAP(_target->getTarget().createAsmParser(*Parser.get(), *_target.get()));
> + TAP(_target->getTarget().createAsmParser(_target->getTargetTriple(),
> + _target->getTargetCPU(),
> + _target->getTargetFeatureString(),
> + *Parser.get()));
> Parser->setTargetParser(*TAP);
> int Res = Parser->Run(false);
> if (Res)
>
> Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=134678&r1=134677&r2=134678&view=diff
> ==============================================================================
> --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original)
> +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Thu Jul 7 20:53:10 2011
> @@ -1817,15 +1817,43 @@
> Info.AsmParser->getValueAsString("AsmParserClassName");
>
> OS << "unsigned " << Info.Target.getName() << ClassName << "::\n"
> - << "ComputeAvailableFeatures(const " << Info.Target.getName()
> - << "Subtarget *Subtarget) const {\n";
> + << "ComputeAvailableFeatures(uint64_t FB) const {\n";
> OS << " unsigned Features = 0;\n";
> for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
> it = Info.SubtargetFeatures.begin(),
> ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
> SubtargetFeatureInfo &SFI = *it->second;
> - OS << " if (" << SFI.TheDef->getValueAsString("CondString")
> - << ")\n";
> +
> + OS << " if (";
> + StringRef Conds = SFI.TheDef->getValueAsString("AssemblerCondString");
> + std::pair<StringRef,StringRef> Comma = Conds.split(',');
> + bool First = true;
> + do {
> + if (!First)
> + OS << " && ";
> +
> + bool Neg = false;
> + StringRef Cond = Comma.first;
> + if (Cond[0] == '!') {
> + Neg = true;
> + Cond = Cond.substr(1);
> + }
> +
> + OS << "((FB & " << Info.Target.getName() << "::" << Cond << ")";
> + if (Neg)
> + OS << " == 0";
> + else
> + OS << " != 0";
> + OS << ")";
> +
> + if (Comma.second.empty())
> + break;
> +
> + First = false;
> + Comma = Comma.second.split(',');
> + } while (true);
> +
> + OS << ")\n";
> OS << " Features |= " << SFI.getEnumName() << ";\n";
> }
> OS << " return Features;\n";
> @@ -2140,8 +2168,7 @@
> OS << "#undef GET_ASSEMBLER_HEADER\n";
> OS << " // This should be included into the middle of the declaration of\n";
> OS << " // your subclasses implementation of TargetAsmParser.\n";
> - OS << " unsigned ComputeAvailableFeatures(const " <<
> - Target.getName() << "Subtarget *Subtarget) const;\n";
> + OS << " unsigned ComputeAvailableFeatures(uint64_t FeatureBits) const;\n";
> OS << " enum MatchResultTy {\n";
> OS << " Match_ConversionFail,\n";
> OS << " Match_InvalidOperand,\n";
>
> Modified: llvm/trunk/utils/TableGen/SubtargetEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/SubtargetEmitter.cpp?rev=134678&r1=134677&r2=134678&view=diff
> ==============================================================================
> --- llvm/trunk/utils/TableGen/SubtargetEmitter.cpp (original)
> +++ llvm/trunk/utils/TableGen/SubtargetEmitter.cpp Thu Jul 7 20:53:10 2011
> @@ -645,12 +645,18 @@
>
> EmitSourceFileHeader("Subtarget Enumeration Source Fragment", OS);
>
> + OS << "\n#ifdef GET_SUBTARGETINFO_ENUM\n";
> + OS << "#undef GET_SUBTARGETINFO_ENUM\n";
> +
> + OS << "namespace llvm {\n";
> + Enumeration(OS, "SubtargetFeature", true);
> + OS << "} // End llvm namespace \n";
> + OS << "#endif // GET_SUBTARGETINFO_ENUM\n\n";
> +
> OS << "\n#ifdef GET_SUBTARGETINFO_MC_DESC\n";
> OS << "#undef GET_SUBTARGETINFO_MC_DESC\n";
>
> OS << "namespace llvm {\n";
> - Enumeration(OS, "SubtargetFeature", true);
> - OS<<"\n";
> unsigned NumFeatures = FeatureKeyValues(OS);
> OS<<"\n";
> unsigned NumProcs = CPUKeyValues(OS);
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20110707/521f58a9/attachment.html>
More information about the llvm-commits
mailing list