<html><head></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space; ">Thanks. Sorry I forgot to commit the clang change. :-(<div><br></div><div>Evan</div><div><br><div><div>On Jul 7, 2011, at 8:16 PM, Chandler Carruth wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite">Fixed in r134680.<br><br><div class="gmail_quote">On Thu, Jul 7, 2011 at 7:39 PM, Nick Lewycky <span dir="ltr"><<a href="mailto:nlewycky@google.com">nlewycky@google.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex;">
<div>Hi Evan, is there a clang half to this change that's coming shortly?</div><div><br></div><div>nlewycky@ducttape:~/llvm/tools/clang/tools/driver$ make</div><div>llvm[0]: Compiling cc1as_main.cpp for Debug+Asserts build</div>
<div>cc1as_main.cpp: In function ‘bool ExecuteAssembler(<unnamed>::AssemblerInvocation&, clang::Diagnostic&)’:</div><div>cc1as_main.cpp:311: error: no matching function for call to ‘llvm::Target::createAsmParser(llvm::MCAsmParser&, llvm::TargetMachine&) const’</div>
<div>/usr/local/google/home/nlewycky/llvm/include/llvm/Target/TargetRegistry.h:302: note: candidates are: llvm::TargetAsmParser* llvm::Target::createAsmParser(llvm::StringRef, llvm::StringRef, llvm::StringRef, llvm::MCAsmParser&) const</div>
<div>make: *** [/usr/local/google/home/nlewycky/llvm/tools/clang/tools/driver/Debug+Asserts/cc1as_main.o] Error 1</div><div><br></div><div>Nick</div><div><br></div><div class="gmail_quote">On 7 July 2011 18:53, Evan Cheng <span dir="ltr"><<a href="mailto:evan.cheng@apple.com" target="_blank" class="cremed">evan.cheng@apple.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: evancheng<br>
Date: Thu Jul 7 20:53:10 2011<br>
New Revision: 134678<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=134678&view=rev" target="_blank" class="cremed">http://llvm.org/viewvc/llvm-project?rev=134678&view=rev</a><br>
Log:<br>
Eliminate asm parser's dependency on TargetMachine:<br>
- Each target asm parser now creates its own MCSubtatgetInfo (if needed).<br>
- Changed AssemblerPredicate to take subtarget features which tablegen uses<br>
to generate asm matcher subtarget feature queries. e.g.<br>
"ModeThumb,FeatureThumb2" is translated to<br>
"(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".<br>
<br>
Modified:<br>
llvm/trunk/include/llvm/Target/Target.td<br>
llvm/trunk/include/llvm/Target/TargetMachine.h<br>
llvm/trunk/include/llvm/Target/TargetRegistry.h<br>
llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp<br>
llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp<br>
llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp<br>
llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.h<br>
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td<br>
llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp<br>
llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp<br>
llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp<br>
llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp<br>
llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h<br>
llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp<br>
llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp<br>
llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp<br>
llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp<br>
llvm/trunk/lib/Target/CBackend/CTargetMachine.h<br>
llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp<br>
llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp<br>
llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h<br>
llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp<br>
llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp<br>
llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp<br>
llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp<br>
llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp<br>
llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp<br>
llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp<br>
llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp<br>
llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp<br>
llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp<br>
llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp<br>
llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp<br>
llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp<br>
llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp<br>
llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp<br>
llvm/trunk/lib/Target/TargetMachine.cpp<br>
llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp<br>
llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp<br>
llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h<br>
llvm/trunk/lib/Target/X86/X86InstrInfo.td<br>
llvm/trunk/lib/Target/X86/X86Subtarget.cpp<br>
llvm/trunk/lib/Target/X86/X86TargetMachine.cpp<br>
llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp<br>
llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp<br>
llvm/trunk/tools/llvm-mc/llvm-mc.cpp<br>
llvm/trunk/tools/lto/LTOModule.cpp<br>
llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp<br>
llvm/trunk/utils/TableGen/SubtargetEmitter.cpp<br>
<br>
Modified: llvm/trunk/include/llvm/Target/Target.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Target.td?rev=134678&r1=134677&r2=134678&view=diff" target="_blank" class="cremed">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Target.td?rev=134678&r1=134677&r2=134678&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/Target/Target.td (original)<br>
+++ llvm/trunk/include/llvm/Target/Target.td Thu Jul 7 20:53:10 2011<br>
@@ -382,6 +382,15 @@<br>
/// matcher, this is true. Targets should set this by inheriting their<br>
/// feature from the AssemblerPredicate class in addition to Predicate.<br>
bit AssemblerMatcherPredicate = 0;<br>
+<br>
+ /// AssemblerCondString - Name of the subtarget feature being tested used<br>
+ /// as alternative condition string used for assembler matcher.<br>
+ /// e.g. "ModeThumb" is translated to "(Bits & ModeThumb) != 0".<br>
+ /// "!ModeThumb" is translated to "(Bits & ModeThumb) == 0".<br>
+ /// It can also list multiple features separated by ",".<br>
+ /// e.g. "ModeThumb,FeatureThumb2" is translated to<br>
+ /// "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".<br>
+ string AssemblerCondString = "";<br>
}<br>
<br>
/// NoHonorSignDependentRounding - This predicate is true if support for<br>
@@ -689,8 +698,9 @@<br>
<br>
/// AssemblerPredicate - This is a Predicate that can be used when the assembler<br>
/// matches instructions and aliases.<br>
-class AssemblerPredicate {<br>
+class AssemblerPredicate<string cond> {<br>
bit AssemblerMatcherPredicate = 1;<br>
+ string AssemblerCondString = cond;<br>
}<br>
<br>
<br>
<br>
Modified: llvm/trunk/include/llvm/Target/TargetMachine.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetMachine.h?rev=134678&r1=134677&r2=134678&view=diff" target="_blank" class="cremed">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetMachine.h?rev=134678&r1=134677&r2=134678&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/Target/TargetMachine.h (original)<br>
+++ llvm/trunk/include/llvm/Target/TargetMachine.h Thu Jul 7 20:53:10 2011<br>
@@ -14,6 +14,7 @@<br>
#ifndef LLVM_TARGET_TARGETMACHINE_H<br>
#define LLVM_TARGET_TARGETMACHINE_H<br>
<br>
+#include "llvm/ADT/StringRef.h"<br>
#include <cassert><br>
#include <string><br>
<br>
@@ -91,7 +92,8 @@<br>
TargetMachine(const TargetMachine &); // DO NOT IMPLEMENT<br>
void operator=(const TargetMachine &); // DO NOT IMPLEMENT<br>
protected: // Can only create subclasses.<br>
- TargetMachine(const Target &);<br>
+ TargetMachine(const Target &T, StringRef TargetTriple,<br>
+ StringRef CPU, StringRef FS);<br>
<br>
/// getSubtargetImpl - virtual method implemented by subclasses that returns<br>
/// a reference to that target's TargetSubtargetInfo-derived member variable.<br>
@@ -100,6 +102,12 @@<br>
/// TheTarget - The Target that this machine was created for.<br>
const Target &TheTarget;<br>
<br>
+ /// TargetTriple, TargetCPU, TargetFS - Triple string, CPU name, and target<br>
+ /// feature strings the TargetMachine instance is created with.<br>
+ std::string TargetTriple;<br>
+ std::string TargetCPU;<br>
+ std::string TargetFS;<br>
+<br>
/// AsmInfo - Contains target specific asm information.<br>
///<br>
const MCAsmInfo *AsmInfo;<br>
@@ -115,6 +123,10 @@<br>
<br>
const Target &getTarget() const { return TheTarget; }<br>
<br>
+ const StringRef getTargetTriple() const { return TargetTriple; }<br>
+ const StringRef getTargetCPU() const { return TargetCPU; }<br>
+ const StringRef getTargetFeatureString() const { return TargetFS; }<br>
+<br>
// Interfaces to the major aspects of target machine information:<br>
// -- Instruction opcode and operand information<br>
// -- Pipelines and scheduling information<br>
@@ -295,10 +307,9 @@<br>
/// implemented with the LLVM target-independent code generator.<br>
///<br>
class LLVMTargetMachine : public TargetMachine {<br>
- std::string TargetTriple;<br>
-<br>
protected: // Can only create subclasses.<br>
- LLVMTargetMachine(const Target &T, const std::string &TargetTriple);<br>
+ LLVMTargetMachine(const Target &T, StringRef TargetTriple,<br>
+ StringRef CPU, StringRef FS);<br>
<br>
private:<br>
/// addCommonCodeGenPasses - Add standard LLVM codegen passes used for<br>
@@ -311,9 +322,6 @@<br>
virtual void setCodeModelForStatic();<br>
<br>
public:<br>
-<br>
- const std::string &getTargetTriple() const { return TargetTriple; }<br>
-<br>
/// addPassesToEmitFile - Add passes to the specified pass manager to get the<br>
/// specified file emitted. Typically this will involve several steps of code<br>
/// generation. If OptLevel is None, the code generator should emit code as<br>
<br>
Modified: llvm/trunk/include/llvm/Target/TargetRegistry.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegistry.h?rev=134678&r1=134677&r2=134678&view=diff" target="_blank" class="cremed">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegistry.h?rev=134678&r1=134677&r2=134678&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/Target/TargetRegistry.h (original)<br>
+++ llvm/trunk/include/llvm/Target/TargetRegistry.h Thu Jul 7 20:53:10 2011<br>
@@ -35,7 +35,6 @@<br>
class MCInstPrinter;<br>
class MCInstrInfo;<br>
class MCRegisterInfo;<br>
- class MCSubtargetInfo;<br>
class MCStreamer;<br>
class TargetAsmBackend;<br>
class TargetAsmLexer;<br>
@@ -70,9 +69,6 @@<br>
StringRef TT);<br>
typedef MCInstrInfo *(*MCInstrInfoCtorFnTy)(void);<br>
typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(void);<br>
- typedef MCSubtargetInfo *(*MCSubtargetInfoCtorFnTy)(StringRef TT,<br>
- StringRef CPU,<br>
- StringRef Features);<br>
typedef TargetMachine *(*TargetMachineCtorTy)(const Target &T,<br>
const std::string &TT,<br>
const std::string &CPU,<br>
@@ -83,8 +79,9 @@<br>
const std::string &TT);<br>
typedef TargetAsmLexer *(*AsmLexerCtorTy)(const Target &T,<br>
const MCAsmInfo &MAI);<br>
- typedef TargetAsmParser *(*AsmParserCtorTy)(const Target &T,MCAsmParser &P,<br>
- TargetMachine &TM);<br>
+ typedef TargetAsmParser *(*AsmParserCtorTy)(const Target &T, StringRef TT,<br>
+ StringRef CPU, StringRef Features,<br>
+ MCAsmParser &P);<br>
typedef MCDisassembler *(*MCDisassemblerCtorTy)(const Target &T);<br>
typedef MCInstPrinter *(*MCInstPrinterCtorTy)(const Target &T,<br>
unsigned SyntaxVariant,<br>
@@ -140,10 +137,6 @@<br>
/// if registered.<br>
MCRegInfoCtorFnTy MCRegInfoCtorFn;<br>
<br>
- /// MCSubtargetInfoCtorFn - Constructor function for this target's<br>
- /// MCSubtargetInfo, if registered.<br>
- MCSubtargetInfoCtorFnTy MCSubtargetInfoCtorFn;<br>
-<br>
/// TargetMachineCtorFn - Construction function for this target's<br>
/// TargetMachine, if registered.<br>
TargetMachineCtorTy TargetMachineCtorFn;<br>
@@ -269,22 +262,6 @@<br>
return MCRegInfoCtorFn();<br>
}<br>
<br>
- /// createMCSubtargetInfo - Create a MCSubtargetInfo implementation.<br>
- ///<br>
- /// \arg Triple - This argument is used to determine the target machine<br>
- /// feature set; it should always be provided. Generally this should be<br>
- /// either the target triple from the module, or the target triple of the<br>
- /// host if that does not exist.<br>
- /// \arg CPU - This specifies the name of the target CPU.<br>
- /// \arg Features - This specifies the string representation of the<br>
- /// additional target features.<br>
- MCSubtargetInfo *createMCSubtargetInfo(StringRef Triple, StringRef CPU,<br>
- StringRef Features) const {<br>
- if (!MCSubtargetInfoCtorFn)<br>
- return 0;<br>
- return MCSubtargetInfoCtorFn(Triple, CPU, Features);<br>
- }<br>
-<br>
/// createTargetMachine - Create a target specific machine implementation<br>
/// for the specified \arg Triple.<br>
///<br>
@@ -322,11 +299,11 @@<br>
///<br>
/// \arg Parser - The target independent parser implementation to use for<br>
/// parsing and lexing.<br>
- TargetAsmParser *createAsmParser(MCAsmParser &Parser,<br>
- TargetMachine &TM) const {<br>
+ TargetAsmParser *createAsmParser(StringRef Triple, StringRef CPU,<br>
+ StringRef Features, MCAsmParser &Parser) const {<br>
if (!AsmParserCtorFn)<br>
return 0;<br>
- return AsmParserCtorFn(*this, Parser, TM);<br>
+ return AsmParserCtorFn(*this, Triple, CPU, Features, Parser);<br>
}<br>
<br>
/// createAsmPrinter - Create a target specific assembly printer pass. This<br>
@@ -528,22 +505,6 @@<br>
T.MCRegInfoCtorFn = Fn;<br>
}<br>
<br>
- /// RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for<br>
- /// the given target.<br>
- ///<br>
- /// Clients are responsible for ensuring that registration doesn't occur<br>
- /// while another thread is attempting to access the registry. Typically<br>
- /// this is done by initializing all targets at program startup.<br>
- ///<br>
- /// @param T - The target being registered.<br>
- /// @param Fn - A function to construct a MCSubtargetInfo for the target.<br>
- static void RegisterMCSubtargetInfo(Target &T,<br>
- Target::MCSubtargetInfoCtorFnTy Fn) {<br>
- // Ignore duplicate registration.<br>
- if (!T.MCSubtargetInfoCtorFn)<br>
- T.MCSubtargetInfoCtorFn = Fn;<br>
- }<br>
-<br>
/// RegisterTargetMachine - Register a TargetMachine implementation for the<br>
/// given target.<br>
///<br>
@@ -820,40 +781,6 @@<br>
}<br>
};<br>
<br>
- /// RegisterMCSubtargetInfo - Helper template for registering a target<br>
- /// subtarget info implementation. This invokes the static "Create" method<br>
- /// on the class to actually do the construction. Usage:<br>
- ///<br>
- /// extern "C" void LLVMInitializeFooTarget() {<br>
- /// extern Target TheFooTarget;<br>
- /// RegisterMCSubtargetInfo<FooMCSubtargetInfo> X(TheFooTarget);<br>
- /// }<br>
- template<class MCSubtargetInfoImpl><br>
- struct RegisterMCSubtargetInfo {<br>
- RegisterMCSubtargetInfo(Target &T) {<br>
- TargetRegistry::RegisterMCSubtargetInfo(T, &Allocator);<br>
- }<br>
- private:<br>
- static MCSubtargetInfo *Allocator(StringRef TT, StringRef CPU,<br>
- StringRef FS) {<br>
- return new MCSubtargetInfoImpl();<br>
- }<br>
- };<br>
-<br>
- /// RegisterMCSubtargetInfoFn - Helper template for registering a target<br>
- /// subtarget info implementation. This invokes the specified function to<br>
- /// do the construction. Usage:<br>
- ///<br>
- /// extern "C" void LLVMInitializeFooTarget() {<br>
- /// extern Target TheFooTarget;<br>
- /// RegisterMCSubtargetInfoFn X(TheFooTarget, TheFunction);<br>
- /// }<br>
- struct RegisterMCSubtargetInfoFn {<br>
- RegisterMCSubtargetInfoFn(Target &T, Target::MCSubtargetInfoCtorFnTy Fn) {<br>
- TargetRegistry::RegisterMCSubtargetInfo(T, Fn);<br>
- }<br>
- };<br>
-<br>
/// RegisterTargetMachine - Helper template for registering a target machine<br>
/// implementation, for use in the target machine initialization<br>
/// function. Usage:<br>
@@ -931,9 +858,10 @@<br>
}<br>
<br>
private:<br>
- static TargetAsmParser *Allocator(const Target &T, MCAsmParser &P,<br>
- TargetMachine &TM) {<br>
- return new AsmParserImpl(T, P, TM);<br>
+ static TargetAsmParser *Allocator(const Target &T, StringRef TT,<br>
+ StringRef CPU, StringRef FS,<br>
+ MCAsmParser &P) {<br>
+ return new AsmParserImpl(T, TT, CPU, FS, P);<br>
}<br>
};<br>
<br>
<br>
Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp?rev=134678&r1=134677&r2=134678&view=diff" target="_blank" class="cremed">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp?rev=134678&r1=134677&r2=134678&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp Thu Jul 7 20:53:10 2011<br>
@@ -111,7 +111,12 @@<br>
OwningPtr<MCAsmParser> Parser(createMCAsmParser(TM.getTarget(), SrcMgr,<br>
OutContext, OutStreamer,<br>
*MAI));<br>
- OwningPtr<TargetAsmParser> TAP(TM.getTarget().createAsmParser(*Parser, TM));<br>
+<br>
+ OwningPtr<TargetAsmParser><br>
+ TAP(TM.getTarget().createAsmParser(TM.getTargetTriple(),<br>
+ TM.getTargetCPU(),<br>
+ TM.getTargetFeatureString(),<br>
+ *Parser));<br>
if (!TAP)<br>
report_fatal_error("Inline asm not supported by this streamer because"<br>
" we don't have an asm parser for this target\n");<br>
<br>
Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff" target="_blank" class="cremed">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Thu Jul 7 20:53:10 2011<br>
@@ -98,10 +98,10 @@<br>
EnableFastISelOption("fast-isel", cl::Hidden,<br>
cl::desc("Enable the \"fast\" instruction selector"));<br>
<br>
-LLVMTargetMachine::LLVMTargetMachine(const Target &T,<br>
- const std::string &Triple)<br>
- : TargetMachine(T), TargetTriple(Triple) {<br>
- AsmInfo = T.createAsmInfo(TargetTriple);<br>
+LLVMTargetMachine::LLVMTargetMachine(const Target &T, StringRef Triple,<br>
+ StringRef CPU, StringRef FS)<br>
+ : TargetMachine(T, Triple, CPU, FS) {<br>
+ AsmInfo = T.createAsmInfo(Triple);<br>
}<br>
<br>
// Set the default code model for the JIT for a generic target.<br>
@@ -143,7 +143,7 @@<br>
TargetAsmBackend *TAB = 0;<br>
if (ShowMCEncoding) {<br>
MCE = getTarget().createCodeEmitter(*this, *Context);<br>
- TAB = getTarget().createAsmBackend(TargetTriple);<br>
+ TAB = getTarget().createAsmBackend(getTargetTriple());<br>
}<br>
<br>
MCStreamer *S = getTarget().createAsmStreamer(*Context, Out,<br>
@@ -160,12 +160,12 @@<br>
// Create the code emitter for the target if it exists. If not, .o file<br>
// emission fails.<br>
MCCodeEmitter *MCE = getTarget().createCodeEmitter(*this, *Context);<br>
- TargetAsmBackend *TAB = getTarget().createAsmBackend(TargetTriple);<br>
+ TargetAsmBackend *TAB = getTarget().createAsmBackend(getTargetTriple());<br>
if (MCE == 0 || TAB == 0)<br>
return true;<br>
<br>
- AsmStreamer.reset(getTarget().createObjectStreamer(TargetTriple, *Context,<br>
- *TAB, Out, MCE,<br>
+ AsmStreamer.reset(getTarget().createObjectStreamer(getTargetTriple(),<br>
+ *Context, *TAB, Out, MCE,<br>
hasMCRelaxAll(),<br>
hasMCNoExecStack()));<br>
AsmStreamer.get()->InitSections();<br>
@@ -241,12 +241,12 @@<br>
// Create the code emitter for the target if it exists. If not, .o file<br>
// emission fails.<br>
MCCodeEmitter *MCE = getTarget().createCodeEmitter(*this, *Ctx);<br>
- TargetAsmBackend *TAB = getTarget().createAsmBackend(TargetTriple);<br>
+ TargetAsmBackend *TAB = getTarget().createAsmBackend(getTargetTriple());<br>
if (MCE == 0 || TAB == 0)<br>
return true;<br>
<br>
OwningPtr<MCStreamer> AsmStreamer;<br>
- AsmStreamer.reset(getTarget().createObjectStreamer(TargetTriple, *Ctx,<br>
+ AsmStreamer.reset(getTarget().createObjectStreamer(getTargetTriple(), *Ctx,<br>
*TAB, Out, MCE,<br>
hasMCRelaxAll(),<br>
hasMCNoExecStack()));<br>
<br>
Modified: llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp?rev=134678&r1=134677&r2=134678&view=diff" target="_blank" class="cremed">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp?rev=134678&r1=134677&r2=134678&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp (original)<br>
+++ llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp Thu Jul 7 20:53:10 2011<br>
@@ -171,7 +171,7 @@<br>
std::string featureString;<br>
TargetMachine.reset(Tgt->createTargetMachine(tripleString, CPU,<br>
featureString));<br>
-<br>
+<br>
const TargetRegisterInfo *registerInfo = TargetMachine->getRegisterInfo();<br>
<br>
if (!registerInfo)<br>
@@ -183,7 +183,7 @@<br>
<br>
if (!AsmInfo)<br>
return;<br>
-<br>
+<br>
Disassembler.reset(Tgt->createMCDisassembler());<br>
<br>
if (!Disassembler)<br>
@@ -371,8 +371,10 @@<br>
OwningPtr<MCAsmParser> genericParser(createMCAsmParser(*Tgt, sourceMgr,<br>
context, *streamer,<br>
*AsmInfo));<br>
- OwningPtr<TargetAsmParser> TargetParser(Tgt->createAsmParser(*genericParser,<br>
- *TargetMachine));<br>
+<br>
+ StringRef triple = tripleFromArch(Key.Arch);<br>
+ OwningPtr<TargetAsmParser> TargetParser(Tgt->createAsmParser(triple, "", "",<br>
+ *genericParser));<br>
<br>
AsmToken OpcodeToken = genericParser->Lex();<br>
AsmToken NextToken = genericParser->Lex(); // consume next token, because specificParser expects us to<br>
<br>
Modified: llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.h?rev=134678&r1=134677&r2=134678&view=diff" target="_blank" class="cremed">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.h?rev=134678&r1=134677&r2=134678&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.h (original)<br>
+++ llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.h Thu Jul 7 20:53:10 2011<br>
@@ -41,6 +41,7 @@<br>
class MCInst;<br>
class MCParsedAsmOperand;<br>
class MCStreamer;<br>
+class MCSubtargetInfo;<br>
template <typename T> class SmallVectorImpl;<br>
class SourceMgr;<br>
class Target;<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=134678&r1=134677&r2=134678&view=diff" target="_blank" class="cremed">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=134678&r1=134677&r2=134678&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Jul 7 20:53:10 2011<br>
@@ -147,35 +147,48 @@<br>
//===----------------------------------------------------------------------===//<br>
// ARM Instruction Predicate Definitions.<br>
//<br>
-def HasV4T : Predicate<"Subtarget->hasV4TOps()">, AssemblerPredicate;<br>
+def HasV4T : Predicate<"Subtarget->hasV4TOps()">,<br>
+ AssemblerPredicate<"HasV4TOps">;<br>
def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;<br>
def HasV5T : Predicate<"Subtarget->hasV5TOps()">;<br>
-def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, AssemblerPredicate;<br>
-def HasV6 : Predicate<"Subtarget->hasV6Ops()">, AssemblerPredicate;<br>
+def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,<br>
+ AssemblerPredicate<"HasV5TEOps">;<br>
+def HasV6 : Predicate<"Subtarget->hasV6Ops()">,<br>
+ AssemblerPredicate<"HasV6Ops">;<br>
def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;<br>
-def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, AssemblerPredicate;<br>
+def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,<br>
+ AssemblerPredicate<"HasV6T2Ops">;<br>
def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;<br>
-def HasV7 : Predicate<"Subtarget->hasV7Ops()">, AssemblerPredicate;<br>
+def HasV7 : Predicate<"Subtarget->hasV7Ops()">,<br>
+ AssemblerPredicate<"HasV7Ops">;<br>
def NoVFP : Predicate<"!Subtarget->hasVFP2()">;<br>
-def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, AssemblerPredicate;<br>
-def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, AssemblerPredicate;<br>
-def HasNEON : Predicate<"Subtarget->hasNEON()">, AssemblerPredicate;<br>
-def HasFP16 : Predicate<"Subtarget->hasFP16()">, AssemblerPredicate;<br>
-def HasDivide : Predicate<"Subtarget->hasDivide()">, AssemblerPredicate;<br>
+def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,<br>
+ AssemblerPredicate<"FeatureVFP2">;<br>
+def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,<br>
+ AssemblerPredicate<"FeatureVFP3">;<br>
+def HasNEON : Predicate<"Subtarget->hasNEON()">,<br>
+ AssemblerPredicate<"FeatureNEON">;<br>
+def HasFP16 : Predicate<"Subtarget->hasFP16()">,<br>
+ AssemblerPredicate<"FeatureFP16">;<br>
+def HasDivide : Predicate<"Subtarget->hasDivide()">,<br>
+ AssemblerPredicate<"FeatureHWDiv">;<br>
def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,<br>
- AssemblerPredicate;<br>
+ AssemblerPredicate<"FeatureT2XtPk">;<br>
def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,<br>
- AssemblerPredicate;<br>
+ AssemblerPredicate<"FeatureDSPThumb2">;<br>
def HasDB : Predicate<"Subtarget->hasDataBarrier()">,<br>
- AssemblerPredicate;<br>
+ AssemblerPredicate<"FeatureDB">;<br>
def HasMP : Predicate<"Subtarget->hasMPExtension()">,<br>
- AssemblerPredicate;<br>
+ AssemblerPredicate<"FeatureMP">;<br>
def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;<br>
def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;<br>
-def IsThumb : Predicate<"Subtarget->isThumb()">, AssemblerPredicate;<br>
+def IsThumb : Predicate<"Subtarget->isThumb()">,<br>
+ AssemblerPredicate<"ModeThumb">;<br>
def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;<br>
-def IsThumb2 : Predicate<"Subtarget->isThumb2()">, AssemblerPredicate;<br>
-def IsARM : Predicate<"!Subtarget->isThumb()">, AssemblerPredicate;<br>
+def IsThumb2 : Predicate<"Subtarget->isThumb2()">,<br>
+ AssemblerPredicate<"ModeThumb,FeatureThumb2">;<br>
+def IsARM : Predicate<"!Subtarget->isThumb()">,<br>
+ AssemblerPredicate<"!ModeThumb">;<br>
def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;<br>
def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff" target="_blank" class="cremed">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Thu Jul 7 20:53:10 2011<br>
@@ -18,9 +18,10 @@<br>
#include "llvm/Support/CommandLine.h"<br>
#include "llvm/ADT/SmallVector.h"<br>
<br>
-#define GET_SUBTARGETINFO_CTOR<br>
+#define GET_SUBTARGETINFO_ENUM<br>
#define GET_SUBTARGETINFO_MC_DESC<br>
#define GET_SUBTARGETINFO_TARGET_DESC<br>
+#define GET_SUBTARGETINFO_CTOR<br>
#include "ARMGenSubtargetInfo.inc"<br>
<br>
using namespace llvm;<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff" target="_blank" class="cremed">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Thu Jul 7 20:53:10 2011<br>
@@ -80,7 +80,7 @@<br>
const std::string &TT,<br>
const std::string &CPU,<br>
const std::string &FS)<br>
- : LLVMTargetMachine(T, TT),<br>
+ : LLVMTargetMachine(T, TT, CPU, FS),<br>
Subtarget(TT, CPU, FS),<br>
JITInfo(),<br>
InstrItins(Subtarget.getInstrItineraryData()) {<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=134678&r1=134677&r2=134678&view=diff" target="_blank" class="cremed">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=134678&r1=134677&r2=134678&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Thu Jul 7 20:53:10 2011<br>
@@ -20,6 +20,7 @@<br>
#include "llvm/MC/MCStreamer.h"<br>
#include "llvm/MC/MCExpr.h"<br>
#include "llvm/MC/MCInst.h"<br>
+#include "llvm/MC/MCSubtargetInfo.h"<br>
#include "llvm/Target/TargetRegistry.h"<br>
#include "llvm/Target/TargetAsmParser.h"<br>
#include "llvm/Support/SourceMgr.h"<br>
@@ -28,6 +29,10 @@<br>
#include "llvm/ADT/StringExtras.h"<br>
#include "llvm/ADT/StringSwitch.h"<br>
#include "llvm/ADT/Twine.h"<br>
+<br>
+#define GET_SUBTARGETINFO_ENUM<br>
+#include "ARMGenSubtargetInfo.inc"<br>
+<br>
using namespace llvm;<br>
<br>
namespace {<br>
@@ -36,7 +41,7 @@<br>
<br>
class ARMAsmParser : public TargetAsmParser {<br>
MCAsmParser &Parser;<br>
- TargetMachine &TM;<br>
+ MCSubtargetInfo *STI;<br>
<br>
MCAsmParser &getParser() const { return Parser; }<br>
MCAsmLexer &getLexer() const { return Parser.getLexer(); }<br>
@@ -79,6 +84,15 @@<br>
void GetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,<br>
bool &CanAcceptPredicationCode);<br>
<br>
+ bool isThumb() const {<br>
+ // FIXME: Can tablegen auto-generate this?<br>
+ return (STI->getFeatureBits() & ARM::ModeThumb) != 0;<br>
+ }<br>
+<br>
+ bool isThumbOne() const {<br>
+ return isThumb() && (STI->getFeatureBits() & ARM::FeatureThumb2) == 0;<br>
+ }<br>
+<br>
/// @name Auto-generated Match Functions<br>
/// {<br>
<br>
@@ -113,13 +127,15 @@<br>
const SmallVectorImpl<MCParsedAsmOperand*> &);<br>
<br>
public:<br>
- ARMAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM)<br>
- : TargetAsmParser(T), Parser(_Parser), TM(_TM) {<br>
- MCAsmParserExtension::Initialize(_Parser);<br>
- // Initialize the set of available features.<br>
- setAvailableFeatures(ComputeAvailableFeatures(<br>
- &TM.getSubtarget<ARMSubtarget>()));<br>
- }<br>
+ ARMAsmParser(const Target &T, StringRef TT, StringRef CPU, StringRef FS,<br>
+ MCAsmParser &_Parser)<br>
+ : TargetAsmParser(T), Parser(_Parser) {<br>
+ STI = ARM_MC::createARMMCSubtargetInfo(TT, CPU, FS);<br>
+<br>
+ MCAsmParserExtension::Initialize(_Parser);<br>
+ // Initialize the set of available features.<br>
+ setAvailableFeatures(ComputeAvailableFeatures(STI->getFeatureBits()));<br>
+ }<br>
<br>
virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,<br>
SmallVectorImpl<MCParsedAsmOperand*> &Operands);<br>
@@ -1852,9 +1868,6 @@<br>
void ARMAsmParser::<br>
GetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,<br>
bool &CanAcceptPredicationCode) {<br>
- bool isThumbOne = TM.getSubtarget<ARMSubtarget>().isThumb1Only();<br>
- bool isThumb = TM.getSubtarget<ARMSubtarget>().isThumb();<br>
-<br>
if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||<br>
Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||<br>
Mnemonic == "smull" || Mnemonic == "add" || Mnemonic == "adc" ||<br>
@@ -1863,7 +1876,7 @@<br>
Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||<br>
Mnemonic == "sbc" || Mnemonic == "mla" || Mnemonic == "umull" ||<br>
Mnemonic == "eor" || Mnemonic == "smlal" ||<br>
- (Mnemonic == "mov" && !isThumbOne)) {<br>
+ (Mnemonic == "mov" && !isThumbOne())) {<br>
CanAcceptCarrySet = true;<br>
} else {<br>
CanAcceptCarrySet = false;<br>
@@ -1880,7 +1893,7 @@<br>
CanAcceptPredicationCode = true;<br>
}<br>
<br>
- if (isThumb)<br>
+ if (isThumb())<br>
if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||<br>
Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")<br>
CanAcceptPredicationCode = false;<br>
@@ -2207,12 +2220,12 @@<br>
// includes Feature_IsThumb or not to match the right instructions. This is<br>
// blocked on the FIXME in llvm-mc.cpp when creating the TargetMachine.<br>
if (Val == 16){<br>
- assert(TM.getSubtarget<ARMSubtarget>().isThumb() &&<br>
+ assert(isThumb() &&<br>
"switching between arm/thumb not yet suppported via .code 16)");<br>
getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);<br>
}<br>
else{<br>
- assert(!TM.getSubtarget<ARMSubtarget>().isThumb() &&<br>
+ assert(!isThumb() &&<br>
"switching between thumb/arm not yet suppported via .code 32)");<br>
getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);<br>
}<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp?rev=134678&r1=134677&r2=134678&view=diff" target="_blank" class="cremed">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp?rev=134678&r1=134677&r2=134678&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp Thu Jul 7 20:53:10 2011<br>
@@ -23,65 +23,12 @@<br>
#define GET_INSTRINFO_MC_DESC<br>
#include "ARMGenInstrInfo.inc"<br>
<br>
+#define GET_SUBTARGETINFO_ENUM<br>
#define GET_SUBTARGETINFO_MC_DESC<br>
#include "ARMGenSubtargetInfo.inc"<br>
<br>
using namespace llvm;<br>
<br>
-MCInstrInfo *createARMMCInstrInfo() {<br>
- MCInstrInfo *X = new MCInstrInfo();<br>
- InitARMMCInstrInfo(X);<br>
- return X;<br>
-}<br>
-<br>
-MCRegisterInfo *createARMMCRegisterInfo() {<br>
- MCRegisterInfo *X = new MCRegisterInfo();<br>
- InitARMMCRegisterInfo(X);<br>
- return X;<br>
-}<br>
-<br>
-MCSubtargetInfo *createARMMCSubtargetInfo(StringRef TT, StringRef CPU,<br>
- StringRef FS) {<br>
- std::string ArchFS = ARM_MC::ParseARMTriple(TT);<br>
- if (!FS.empty()) {<br>
- if (!ArchFS.empty())<br>
- ArchFS = ArchFS + "," + FS.str();<br>
- else<br>
- ArchFS = FS;<br>
- }<br>
-<br>
- MCSubtargetInfo *X = new MCSubtargetInfo();<br>
- InitARMMCSubtargetInfo(X, CPU, ArchFS);<br>
- return X;<br>
-}<br>
-<br>
-// Force static initialization.<br>
-extern "C" void LLVMInitializeARMMCInstrInfo() {<br>
- RegisterMCInstrInfo<MCInstrInfo> X(TheARMTarget);<br>
- RegisterMCInstrInfo<MCInstrInfo> Y(TheThumbTarget);<br>
-<br>
- TargetRegistry::RegisterMCInstrInfo(TheARMTarget, createARMMCInstrInfo);<br>
- TargetRegistry::RegisterMCInstrInfo(TheThumbTarget, createARMMCInstrInfo);<br>
-}<br>
-<br>
-extern "C" void LLVMInitializeARMMCRegInfo() {<br>
- RegisterMCRegInfo<MCRegisterInfo> X(TheARMTarget);<br>
- RegisterMCRegInfo<MCRegisterInfo> Y(TheThumbTarget);<br>
-<br>
- TargetRegistry::RegisterMCRegInfo(TheARMTarget, createARMMCRegisterInfo);<br>
- TargetRegistry::RegisterMCRegInfo(TheThumbTarget, createARMMCRegisterInfo);<br>
-}<br>
-<br>
-extern "C" void LLVMInitializeARMMCSubtargetInfo() {<br>
- RegisterMCSubtargetInfo<MCSubtargetInfo> X(TheARMTarget);<br>
- RegisterMCSubtargetInfo<MCSubtargetInfo> Y(TheThumbTarget);<br>
-<br>
- TargetRegistry::RegisterMCSubtargetInfo(TheARMTarget,<br>
- createARMMCSubtargetInfo);<br>
- TargetRegistry::RegisterMCSubtargetInfo(TheThumbTarget,<br>
- createARMMCSubtargetInfo);<br>
-}<br>
-<br>
std::string ARM_MC::ParseARMTriple(StringRef TT) {<br>
// Set the boolean corresponding to the current target triple, or the default<br>
// if one cannot be determined, to true.<br>
@@ -135,3 +82,47 @@<br>
<br>
return ARMArchFeature;<br>
}<br>
+<br>
+MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(StringRef TT, StringRef CPU,<br>
+ StringRef FS) {<br>
+ std::string ArchFS = ARM_MC::ParseARMTriple(TT);<br>
+ if (!FS.empty()) {<br>
+ if (!ArchFS.empty())<br>
+ ArchFS = ArchFS + "," + FS.str();<br>
+ else<br>
+ ArchFS = FS;<br>
+ }<br>
+<br>
+ MCSubtargetInfo *X = new MCSubtargetInfo();<br>
+ InitARMMCSubtargetInfo(X, CPU, ArchFS);<br>
+ return X;<br>
+}<br>
+<br>
+MCInstrInfo *createARMMCInstrInfo() {<br>
+ MCInstrInfo *X = new MCInstrInfo();<br>
+ InitARMMCInstrInfo(X);<br>
+ return X;<br>
+}<br>
+<br>
+MCRegisterInfo *createARMMCRegisterInfo() {<br>
+ MCRegisterInfo *X = new MCRegisterInfo();<br>
+ InitARMMCRegisterInfo(X);<br>
+ return X;<br>
+}<br>
+<br>
+// Force static initialization.<br>
+extern "C" void LLVMInitializeARMMCInstrInfo() {<br>
+ RegisterMCInstrInfo<MCInstrInfo> X(TheARMTarget);<br>
+ RegisterMCInstrInfo<MCInstrInfo> Y(TheThumbTarget);<br>
+<br>
+ TargetRegistry::RegisterMCInstrInfo(TheARMTarget, createARMMCInstrInfo);<br>
+ TargetRegistry::RegisterMCInstrInfo(TheThumbTarget, createARMMCInstrInfo);<br>
+}<br>
+<br>
+extern "C" void LLVMInitializeARMMCRegInfo() {<br>
+ RegisterMCRegInfo<MCRegisterInfo> X(TheARMTarget);<br>
+ RegisterMCRegInfo<MCRegisterInfo> Y(TheThumbTarget);<br>
+<br>
+ TargetRegistry::RegisterMCRegInfo(TheARMTarget, createARMMCRegisterInfo);<br>
+ TargetRegistry::RegisterMCRegInfo(TheThumbTarget, createARMMCRegisterInfo);<br>
+}<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h?rev=134678&r1=134677&r2=134678&view=diff" target="_blank" class="cremed">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h?rev=134678&r1=134677&r2=134678&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h (original)<br>
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h Thu Jul 7 20:53:10 2011<br>
@@ -17,6 +17,7 @@<br>
#include <string><br>
<br>
namespace llvm {<br>
+class MCSubtargetInfo;<br>
class Target;<br>
class StringRef;<br>
<br>
@@ -24,6 +25,12 @@<br>
<br>
namespace ARM_MC {<br>
std::string ParseARMTriple(StringRef TT);<br>
+<br>
+ /// createARMMCSubtargetInfo - Create a ARM MCSubtargetInfo instance.<br>
+ /// This is exposed so Asm parser, etc. do not need to go through<br>
+ /// TargetRegistry.<br>
+ MCSubtargetInfo *createARMMCSubtargetInfo(StringRef TT, StringRef CPU,<br>
+ StringRef FS);<br>
}<br>
<br>
} // End llvm namespace<br>
<br>
Modified: llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff" target="_blank" class="cremed">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp (original)<br>
+++ llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp Thu Jul 7 20:53:10 2011<br>
@@ -14,9 +14,10 @@<br>
#include "AlphaSubtarget.h"<br>
#include "Alpha.h"<br>
<br>
-#define GET_SUBTARGETINFO_CTOR<br>
+#define GET_SUBTARGETINFO_ENUM<br>
#define GET_SUBTARGETINFO_MC_DESC<br>
#define GET_SUBTARGETINFO_TARGET_DESC<br>
+#define GET_SUBTARGETINFO_CTOR<br>
#include "AlphaGenSubtargetInfo.inc"<br>
<br>
using namespace llvm;<br>
<br>
Modified: llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff" target="_blank" class="cremed">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp (original)<br>
+++ llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp Thu Jul 7 20:53:10 2011<br>
@@ -27,7 +27,7 @@<br>
AlphaTargetMachine::AlphaTargetMachine(const Target &T, const std::string &TT,<br>
const std::string &CPU,<br>
const std::string &FS)<br>
- : LLVMTargetMachine(T, TT),<br>
+ : LLVMTargetMachine(T, TT, CPU, FS),<br>
DataLayout("e-f128:128:128-n64"),<br>
FrameLowering(Subtarget),<br>
Subtarget(TT, CPU, FS),<br>
<br>
Modified: llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff" target="_blank" class="cremed">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp (original)<br>
+++ llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp Thu Jul 7 20:53:10 2011<br>
@@ -13,9 +13,10 @@<br>
<br>
#include "BlackfinSubtarget.h"<br>
<br>
-#define GET_SUBTARGETINFO_CTOR<br>
+#define GET_SUBTARGETINFO_ENUM<br>
#define GET_SUBTARGETINFO_MC_DESC<br>
#define GET_SUBTARGETINFO_TARGET_DESC<br>
+#define GET_SUBTARGETINFO_CTOR<br>
#include "BlackfinGenSubtargetInfo.inc"<br>
<br>
using namespace llvm;<br>
<br>
Modified: llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff" target="_blank" class="cremed">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp (original)<br>
+++ llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp Thu Jul 7 20:53:10 2011<br>
@@ -28,7 +28,7 @@<br>
const std::string &TT,<br>
const std::string &CPU,<br>
const std::string &FS)<br>
- : LLVMTargetMachine(T, TT),<br>
+ : LLVMTargetMachine(T, TT, CPU, FS),<br>
DataLayout("e-p:32:32-i64:32-f64:32-n32"),<br>
Subtarget(TT, CPU, FS),<br>
TLInfo(*this),<br>
<br>
Modified: llvm/trunk/lib/Target/CBackend/CTargetMachine.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CTargetMachine.h?rev=134678&r1=134677&r2=134678&view=diff" target="_blank" class="cremed">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CTargetMachine.h?rev=134678&r1=134677&r2=134678&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/CBackend/CTargetMachine.h (original)<br>
+++ llvm/trunk/lib/Target/CBackend/CTargetMachine.h Thu Jul 7 20:53:10 2011<br>
@@ -22,7 +22,7 @@<br>
struct CTargetMachine : public TargetMachine {<br>
CTargetMachine(const Target &T, const std::string &TT,<br>
const std::string &CPU, const std::string &FS)<br>
- : TargetMachine(T) {}<br>
+ : TargetMachine(T, TT, CPU, FS) {}<br>
<br>
virtual bool addPassesToEmitFile(PassManagerBase &PM,<br>
formatted_raw_ostream &Out,<br>
<br>
Modified: llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff" target="_blank" class="cremed">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp (original)<br>
+++ llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp Thu Jul 7 20:53:10 2011<br>
@@ -13,12 +13,13 @@<br>
<br>
#include "SPUSubtarget.h"<br>
#include "SPU.h"<br>
-#include "llvm/ADT/SmallVector.h"<br>
#include "SPURegisterInfo.h"<br>
+#include "llvm/ADT/SmallVector.h"<br>
<br>
-#define GET_SUBTARGETINFO_CTOR<br>
+#define GET_SUBTARGETINFO_ENUM<br>
#define GET_SUBTARGETINFO_MC_DESC<br>
#define GET_SUBTARGETINFO_TARGET_DESC<br>
+#define GET_SUBTARGETINFO_CTOR<br>
#include "SPUGenSubtargetInfo.inc"<br>
<br>
using namespace llvm;<br>
<br>
Modified: llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff" target="_blank" class="cremed">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp (original)<br>
+++ llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp Thu Jul 7 20:53:10 2011<br>
@@ -36,7 +36,7 @@<br>
<br>
SPUTargetMachine::SPUTargetMachine(const Target &T, const std::string &TT,<br>
const std::string &CPU,const std::string &FS)<br>
- : LLVMTargetMachine(T, TT),<br>
+ : LLVMTargetMachine(T, TT, CPU, FS),<br>
Subtarget(TT, CPU, FS),<br>
DataLayout(Subtarget.getTargetDataString()),<br>
InstrInfo(*this),<br>
<br>
Modified: llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h?rev=134678&r1=134677&r2=134678&view=diff" target="_blank" class="cremed">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h?rev=134678&r1=134677&r2=134678&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h (original)<br>
+++ llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h Thu Jul 7 20:53:10 2011<br>
@@ -24,7 +24,7 @@<br>
struct CPPTargetMachine : public TargetMachine {<br>
CPPTargetMachine(const Target &T, const std::string &TT,<br>
const std::string &CPU, const std::string &FS)<br>
- : TargetMachine(T) {}<br>
+ : TargetMachine(T, TT, CPU, FS) {}<br>
<br>
virtual bool addPassesToEmitFile(PassManagerBase &PM,<br>
formatted_raw_ostream &Out,<br>
<br>
Modified: llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp?rev=134678&r1=134677&r2=134678&view=diff" target="_blank" class="cremed">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp?rev=134678&r1=134677&r2=134678&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp (original)<br>
+++ llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp Thu Jul 7 20:53:10 2011<br>
@@ -32,7 +32,6 @@<br>
<br>
class MBlazeAsmParser : public TargetAsmParser {<br>
MCAsmParser &Parser;<br>
- TargetMachine &TM;<br>
<br>
MCAsmParser &getParser() const { return Parser; }<br>
MCAsmLexer &getLexer() const { return Parser.getLexer(); }<br>
@@ -64,8 +63,9 @@<br>
<br>
<br>
public:<br>
- MBlazeAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM)<br>
- : TargetAsmParser(T), Parser(_Parser), TM(_TM) {}<br>
+ MBlazeAsmParser(const Target &T, StringRef TT, StringRef CPU, StringRef FS,<br>
+ MCAsmParser &_Parser)<br>
+ : TargetAsmParser(T), Parser(_Parser) {}<br>
<br>
virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,<br>
SmallVectorImpl<MCParsedAsmOperand*> &Operands);<br>
<br>
Modified: llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff" target="_blank" class="cremed">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp (original)<br>
+++ llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp Thu Jul 7 20:53:10 2011<br>
@@ -16,9 +16,10 @@<br>
#include "MBlazeRegisterInfo.h"<br>
#include "llvm/Support/CommandLine.h"<br>
<br>
-#define GET_SUBTARGETINFO_CTOR<br>
+#define GET_SUBTARGETINFO_ENUM<br>
#define GET_SUBTARGETINFO_MC_DESC<br>
#define GET_SUBTARGETINFO_TARGET_DESC<br>
+#define GET_SUBTARGETINFO_CTOR<br>
#include "MBlazeGenSubtargetInfo.inc"<br>
<br>
using namespace llvm;<br>
@@ -61,4 +62,3 @@<br>
CriticalPathRCs.push_back(&MBlaze::GPRRegClass);<br>
return HasItin && OptLevel >= CodeGenOpt::Default;<br>
}<br>
-<br>
<br>
Modified: llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff" target="_blank" class="cremed">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp (original)<br>
+++ llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp Thu Jul 7 20:53:10 2011<br>
@@ -81,7 +81,7 @@<br>
MBlazeTargetMachine::<br>
MBlazeTargetMachine(const Target &T, const std::string &TT,<br>
const std::string &CPU, const std::string &FS):<br>
- LLVMTargetMachine(T, TT),<br>
+ LLVMTargetMachine(T, TT, CPU, FS),<br>
Subtarget(TT, CPU, FS),<br>
DataLayout("E-p:32:32:32-i8:8:8-i16:16:16"),<br>
InstrInfo(*this),<br>
<br>
Modified: llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff" target="_blank" class="cremed">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp (original)<br>
+++ llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp Thu Jul 7 20:53:10 2011<br>
@@ -14,9 +14,10 @@<br>
#include "MSP430Subtarget.h"<br>
#include "MSP430.h"<br>
<br>
-#define GET_SUBTARGETINFO_CTOR<br>
+#define GET_SUBTARGETINFO_ENUM<br>
#define GET_SUBTARGETINFO_MC_DESC<br>
#define GET_SUBTARGETINFO_TARGET_DESC<br>
+#define GET_SUBTARGETINFO_CTOR<br>
#include "MSP430GenSubtargetInfo.inc"<br>
<br>
using namespace llvm;<br>
<br>
Modified: llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff" target="_blank" class="cremed">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp (original)<br>
+++ llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp Thu Jul 7 20:53:10 2011<br>
@@ -30,7 +30,7 @@<br>
const std::string &TT,<br>
const std::string &CPU,<br>
const std::string &FS)<br>
- : LLVMTargetMachine(T, TT),<br>
+ : LLVMTargetMachine(T, TT, CPU, FS),<br>
Subtarget(TT, CPU, FS),<br>
// FIXME: Check TargetData string.<br>
DataLayout("e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"),<br>
<br>
Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff" target="_blank" class="cremed">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp (original)<br>
+++ llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp Thu Jul 7 20:53:10 2011<br>
@@ -14,9 +14,10 @@<br>
#include "MipsSubtarget.h"<br>
#include "Mips.h"<br>
<br>
-#define GET_SUBTARGETINFO_CTOR<br>
+#define GET_SUBTARGETINFO_ENUM<br>
#define GET_SUBTARGETINFO_MC_DESC<br>
#define GET_SUBTARGETINFO_TARGET_DESC<br>
+#define GET_SUBTARGETINFO_CTOR<br>
#include "MipsGenSubtargetInfo.inc"<br>
<br>
using namespace llvm;<br>
<br>
Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff" target="_blank" class="cremed">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp (original)<br>
+++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp Thu Jul 7 20:53:10 2011<br>
@@ -37,7 +37,7 @@<br>
MipsTargetMachine(const Target &T, const std::string &TT,<br>
const std::string &CPU, const std::string &FS,<br>
bool isLittle=false):<br>
- LLVMTargetMachine(T, TT),<br>
+ LLVMTargetMachine(T, TT, CPU, FS),<br>
Subtarget(TT, CPU, FS, isLittle),<br>
DataLayout(isLittle ?<br>
std::string("e-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32") :<br>
<br>
Modified: llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff" target="_blank" class="cremed">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp (original)<br>
+++ llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp Thu Jul 7 20:53:10 2011<br>
@@ -14,9 +14,10 @@<br>
#include "PTXSubtarget.h"<br>
#include "llvm/Support/ErrorHandling.h"<br>
<br>
-#define GET_SUBTARGETINFO_CTOR<br>
+#define GET_SUBTARGETINFO_ENUM<br>
#define GET_SUBTARGETINFO_MC_DESC<br>
#define GET_SUBTARGETINFO_TARGET_DESC<br>
+#define GET_SUBTARGETINFO_CTOR<br>
#include "PTXGenSubtargetInfo.inc"<br>
<br>
using namespace llvm;<br>
<br>
Modified: llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff" target="_blank" class="cremed">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp (original)<br>
+++ llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp Thu Jul 7 20:53:10 2011<br>
@@ -55,7 +55,7 @@<br>
const std::string &CPU,<br>
const std::string &FS,<br>
bool is64Bit)<br>
- : LLVMTargetMachine(T, TT),<br>
+ : LLVMTargetMachine(T, TT, CPU, FS),<br>
DataLayout(is64Bit ? DataLayout64 : DataLayout32),<br>
Subtarget(TT, CPU, FS, is64Bit),<br>
FrameLowering(Subtarget),<br>
<br>
Modified: llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff" target="_blank" class="cremed">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp (original)<br>
+++ llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp Thu Jul 7 20:53:10 2011<br>
@@ -17,9 +17,10 @@<br>
#include "llvm/Target/TargetMachine.h"<br>
#include <cstdlib><br>
<br>
-#define GET_SUBTARGETINFO_CTOR<br>
+#define GET_SUBTARGETINFO_ENUM<br>
#define GET_SUBTARGETINFO_MC_DESC<br>
#define GET_SUBTARGETINFO_TARGET_DESC<br>
+#define GET_SUBTARGETINFO_CTOR<br>
#include "PPCGenSubtargetInfo.inc"<br>
<br>
using namespace llvm;<br>
<br>
Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff" target="_blank" class="cremed">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp (original)<br>
+++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp Thu Jul 7 20:53:10 2011<br>
@@ -69,7 +69,7 @@<br>
PPCTargetMachine::PPCTargetMachine(const Target &T, const std::string &TT,<br>
const std::string &CPU,<br>
const std::string &FS, bool is64Bit)<br>
- : LLVMTargetMachine(T, TT),<br>
+ : LLVMTargetMachine(T, TT, CPU, FS),<br>
Subtarget(TT, CPU, FS, is64Bit),<br>
DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this),<br>
FrameLowering(Subtarget), JITInfo(*this, is64Bit),<br>
<br>
Modified: llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff" target="_blank" class="cremed">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp (original)<br>
+++ llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp Thu Jul 7 20:53:10 2011<br>
@@ -13,9 +13,10 @@<br>
<br>
#include "SparcSubtarget.h"<br>
<br>
-#define GET_SUBTARGETINFO_CTOR<br>
+#define GET_SUBTARGETINFO_ENUM<br>
#define GET_SUBTARGETINFO_MC_DESC<br>
#define GET_SUBTARGETINFO_TARGET_DESC<br>
+#define GET_SUBTARGETINFO_CTOR<br>
#include "SparcGenSubtargetInfo.inc"<br>
<br>
using namespace llvm;<br>
<br>
Modified: llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff" target="_blank" class="cremed">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp (original)<br>
+++ llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp Thu Jul 7 20:53:10 2011<br>
@@ -32,7 +32,7 @@<br>
SparcTargetMachine::SparcTargetMachine(const Target &T, const std::string &TT,<br>
const std::string &CPU,<br>
const std::string &FS, bool is64bit)<br>
- : LLVMTargetMachine(T, TT),<br>
+ : LLVMTargetMachine(T, TT, CPU, FS),<br>
Subtarget(TT, CPU, FS, is64bit),<br>
DataLayout(Subtarget.getDataLayout()),<br>
TLInfo(*this), TSInfo(*this), InstrInfo(Subtarget),<br>
<br>
Modified: llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff" target="_blank" class="cremed">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp (original)<br>
+++ llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp Thu Jul 7 20:53:10 2011<br>
@@ -16,9 +16,10 @@<br>
#include "llvm/GlobalValue.h"<br>
#include "llvm/Target/TargetMachine.h"<br>
<br>
-#define GET_SUBTARGETINFO_CTOR<br>
+#define GET_SUBTARGETINFO_ENUM<br>
#define GET_SUBTARGETINFO_MC_DESC<br>
#define GET_SUBTARGETINFO_TARGET_DESC<br>
+#define GET_SUBTARGETINFO_CTOR<br>
#include "SystemZGenSubtargetInfo.inc"<br>
<br>
using namespace llvm;<br>
<br>
Modified: llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff" target="_blank" class="cremed">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp (original)<br>
+++ llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp Thu Jul 7 20:53:10 2011<br>
@@ -26,7 +26,7 @@<br>
const std::string &TT,<br>
const std::string &CPU,<br>
const std::string &FS)<br>
- : LLVMTargetMachine(T, TT),<br>
+ : LLVMTargetMachine(T, TT, CPU, FS),<br>
Subtarget(TT, CPU, FS),<br>
DataLayout("E-p:64:64:64-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:32"<br>
"-f64:64:64-f128:128:128-a0:16:16-n32:64"),<br>
<br>
Modified: llvm/trunk/lib/Target/TargetMachine.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff" target="_blank" class="cremed">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/TargetMachine.cpp (original)<br>
+++ llvm/trunk/lib/Target/TargetMachine.cpp Thu Jul 7 20:53:10 2011<br>
@@ -216,8 +216,9 @@<br>
// TargetMachine Class<br>
//<br>
<br>
-TargetMachine::TargetMachine(const Target &T)<br>
- : TheTarget(T), AsmInfo(0),<br>
+TargetMachine::TargetMachine(const Target &T,<br>
+ StringRef TT, StringRef CPU, StringRef FS)<br>
+ : TheTarget(T), TargetTriple(TT), TargetCPU(CPU), TargetFS(FS), AsmInfo(0),<br>
MCRelaxAll(false),<br>
MCNoExecStack(false),<br>
MCSaveTempLabels(false),<br>
<br>
Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=134678&r1=134677&r2=134678&view=diff" target="_blank" class="cremed">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=134678&r1=134677&r2=134678&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Thu Jul 7 20:53:10 2011<br>
@@ -15,6 +15,7 @@<br>
#include "llvm/MC/MCStreamer.h"<br>
#include "llvm/MC/MCExpr.h"<br>
#include "llvm/MC/MCInst.h"<br>
+#include "llvm/MC/MCSubtargetInfo.h"<br>
#include "llvm/MC/MCParser/MCAsmLexer.h"<br>
#include "llvm/MC/MCParser/MCAsmParser.h"<br>
#include "llvm/MC/MCParser/MCParsedAsmOperand.h"<br>
@@ -25,6 +26,10 @@<br>
#include "llvm/ADT/Twine.h"<br>
#include "llvm/Support/SourceMgr.h"<br>
#include "llvm/Support/raw_ostream.h"<br>
+<br>
+#define GET_SUBTARGETINFO_ENUM<br>
+#include "X86GenSubtargetInfo.inc"<br>
+<br>
using namespace llvm;<br>
<br>
namespace {<br>
@@ -32,10 +37,7 @@<br>
<br>
class X86ATTAsmParser : public TargetAsmParser {<br>
MCAsmParser &Parser;<br>
- TargetMachine &TM;<br>
-<br>
-protected:<br>
- unsigned Is64Bit : 1;<br>
+ MCSubtargetInfo *STI;<br>
<br>
private:<br>
MCAsmParser &getParser() const { return Parser; }<br>
@@ -61,6 +63,11 @@<br>
/// or %es:(%edi) in 32bit mode.<br>
bool isDstOp(X86Operand &Op);<br>
<br>
+ bool is64Bit() {<br>
+ // FIXME: Can tablegen auto-generate this?<br>
+ return (STI->getFeatureBits() & X86::Mode64Bit) != 0;<br>
+ }<br>
+<br>
/// @name Auto-generated Matcher Functions<br>
/// {<br>
<br>
@@ -70,12 +77,13 @@<br>
/// }<br>
<br>
public:<br>
- X86ATTAsmParser(const Target &T, MCAsmParser &parser, TargetMachine &TM)<br>
- : TargetAsmParser(T), Parser(parser), TM(TM) {<br>
+ X86ATTAsmParser(const Target &T, StringRef TT, StringRef CPU, StringRef FS,<br>
+ MCAsmParser &parser)<br>
+ : TargetAsmParser(T), Parser(parser) {<br>
+ STI = X86_MC::createX86MCSubtargetInfo(TT, CPU, FS);<br>
<br>
// Initialize the set of available features.<br>
- setAvailableFeatures(ComputeAvailableFeatures(<br>
- &TM.getSubtarget<X86Subtarget>()));<br>
+ setAvailableFeatures(ComputeAvailableFeatures(STI->getFeatureBits()));<br>
}<br>
virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);<br>
<br>
@@ -84,23 +92,6 @@<br>
<br>
virtual bool ParseDirective(AsmToken DirectiveID);<br>
};<br>
-<br>
-class X86_32ATTAsmParser : public X86ATTAsmParser {<br>
-public:<br>
- X86_32ATTAsmParser(const Target &T, MCAsmParser &Parser, TargetMachine &TM)<br>
- : X86ATTAsmParser(T, Parser, TM) {<br>
- Is64Bit = false;<br>
- }<br>
-};<br>
-<br>
-class X86_64ATTAsmParser : public X86ATTAsmParser {<br>
-public:<br>
- X86_64ATTAsmParser(const Target &T, MCAsmParser &Parser, TargetMachine &TM)<br>
- : X86ATTAsmParser(T, Parser, TM) {<br>
- Is64Bit = true;<br>
- }<br>
-};<br>
-<br>
} // end anonymous namespace<br>
<br>
/// @name Auto-generated Match Functions<br>
@@ -365,7 +356,7 @@<br>
} // end anonymous namespace.<br>
<br>
bool X86ATTAsmParser::isSrcOp(X86Operand &Op) {<br>
- unsigned basereg = Is64Bit ? X86::RSI : X86::ESI;<br>
+ unsigned basereg = is64Bit() ? X86::RSI : X86::ESI;<br>
<br>
return (Op.isMem() &&<br>
(Op.Mem.SegReg == 0 || Op.Mem.SegReg == X86::DS) &&<br>
@@ -375,7 +366,7 @@<br>
}<br>
<br>
bool X86ATTAsmParser::isDstOp(X86Operand &Op) {<br>
- unsigned basereg = Is64Bit ? X86::RDI : X86::EDI;<br>
+ unsigned basereg = is64Bit() ? X86::RDI : X86::EDI;<br>
<br>
return Op.isMem() && Op.Mem.SegReg == X86::ES &&<br>
isa<MCConstantExpr>(Op.Mem.Disp) &&<br>
@@ -406,7 +397,7 @@<br>
// FIXME: This should be done using Requires<In32BitMode> and<br>
// Requires<In64BitMode> so "eiz" usage in 64-bit instructions<br>
// can be also checked.<br>
- if (RegNo == X86::RIZ && !Is64Bit)<br>
+ if (RegNo == X86::RIZ && !is64Bit())<br>
return Error(Tok.getLoc(), "riz register in 64-bit mode only");<br>
<br>
// Parse "%st" as "%st(0)" and "%st(1)", which is multiple tokens.<br>
@@ -826,7 +817,7 @@<br>
// Transform "movs[bwl] %ds:(%esi), %es:(%edi)" into "movs[bwl]"<br>
if (Name.startswith("movs") && Operands.size() == 3 &&<br>
(Name == "movsb" || Name == "movsw" || Name == "movsl" ||<br>
- (Is64Bit && Name == "movsq"))) {<br>
+ (is64Bit() && Name == "movsq"))) {<br>
X86Operand &Op = *(X86Operand*)Operands.begin()[1];<br>
X86Operand &Op2 = *(X86Operand*)Operands.begin()[2];<br>
if (isSrcOp(Op) && isDstOp(Op2)) {<br>
@@ -839,7 +830,7 @@<br>
// Transform "lods[bwl] %ds:(%esi),{%al,%ax,%eax,%rax}" into "lods[bwl]"<br>
if (Name.startswith("lods") && Operands.size() == 3 &&<br>
(Name == "lods" || Name == "lodsb" || Name == "lodsw" ||<br>
- Name == "lodsl" || (Is64Bit && Name == "lodsq"))) {<br>
+ Name == "lodsl" || (is64Bit() && Name == "lodsq"))) {<br>
X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);<br>
X86Operand *Op2 = static_cast<X86Operand*>(Operands[2]);<br>
if (isSrcOp(*Op1) && Op2->isReg()) {<br>
@@ -869,7 +860,7 @@<br>
// Transform "stos[bwl] {%al,%ax,%eax,%rax},%es:(%edi)" into "stos[bwl]"<br>
if (Name.startswith("stos") && Operands.size() == 3 &&<br>
(Name == "stos" || Name == "stosb" || Name == "stosw" ||<br>
- Name == "stosl" || (Is64Bit && Name == "stosq"))) {<br>
+ Name == "stosl" || (is64Bit() && Name == "stosq"))) {<br>
X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);<br>
X86Operand *Op2 = static_cast<X86Operand*>(Operands[2]);<br>
if (isDstOp(*Op2) && Op1->isReg()) {<br>
@@ -1144,8 +1135,8 @@<br>
<br>
// Force static initialization.<br>
extern "C" void LLVMInitializeX86AsmParser() {<br>
- RegisterAsmParser<X86_32ATTAsmParser> X(TheX86_32Target);<br>
- RegisterAsmParser<X86_64ATTAsmParser> Y(TheX86_64Target);<br>
+ RegisterAsmParser<X86ATTAsmParser> X(TheX86_32Target);<br>
+ RegisterAsmParser<X86ATTAsmParser> Y(TheX86_64Target);<br>
LLVMInitializeX86AsmLexer();<br>
}<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp?rev=134678&r1=134677&r2=134678&view=diff" target="_blank" class="cremed">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp?rev=134678&r1=134677&r2=134678&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp Thu Jul 7 20:53:10 2011<br>
@@ -25,6 +25,7 @@<br>
#define GET_INSTRINFO_MC_DESC<br>
#include "X86GenInstrInfo.inc"<br>
<br>
+#define GET_SUBTARGETINFO_ENUM<br>
#define GET_SUBTARGETINFO_MC_DESC<br>
#include "X86GenSubtargetInfo.inc"<br>
<br>
@@ -35,7 +36,7 @@<br>
Triple TheTriple(TT);<br>
if (TheTriple.getArch() == Triple::x86_64)<br>
return "+64bit-mode";<br>
- return "";<br>
+ return "-64bit-mode";<br>
}<br>
<br>
/// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the<br>
@@ -128,20 +129,8 @@<br>
return false;<br>
}<br>
<br>
-MCInstrInfo *createX86MCInstrInfo() {<br>
- MCInstrInfo *X = new MCInstrInfo();<br>
- InitX86MCInstrInfo(X);<br>
- return X;<br>
-}<br>
-<br>
-MCRegisterInfo *createX86MCRegisterInfo() {<br>
- MCRegisterInfo *X = new MCRegisterInfo();<br>
- InitX86MCRegisterInfo(X);<br>
- return X;<br>
-}<br>
-<br>
-MCSubtargetInfo *createX86MCSubtargetInfo(StringRef TT, StringRef CPU,<br>
- StringRef FS) {<br>
+MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(StringRef TT, StringRef CPU,<br>
+ StringRef FS) {<br>
std::string ArchFS = X86_MC::ParseX86Triple(TT);<br>
if (!FS.empty()) {<br>
if (!ArchFS.empty())<br>
@@ -159,7 +148,19 @@<br>
ArchFS = "+64bit-mode";<br>
<br>
MCSubtargetInfo *X = new MCSubtargetInfo();<br>
- InitX86MCSubtargetInfo(X, CPU, ArchFS);<br>
+ InitX86MCSubtargetInfo(X, CPUName, ArchFS);<br>
+ return X;<br>
+}<br>
+<br>
+MCInstrInfo *createX86MCInstrInfo() {<br>
+ MCInstrInfo *X = new MCInstrInfo();<br>
+ InitX86MCInstrInfo(X);<br>
+ return X;<br>
+}<br>
+<br>
+MCRegisterInfo *createX86MCRegisterInfo() {<br>
+ MCRegisterInfo *X = new MCRegisterInfo();<br>
+ InitX86MCRegisterInfo(X);<br>
return X;<br>
}<br>
<br>
@@ -179,13 +180,3 @@<br>
TargetRegistry::RegisterMCRegInfo(TheX86_32Target, createX86MCRegisterInfo);<br>
TargetRegistry::RegisterMCRegInfo(TheX86_64Target, createX86MCRegisterInfo);<br>
}<br>
-<br>
-extern "C" void LLVMInitializeX86MCSubtargetInfo() {<br>
- RegisterMCSubtargetInfo<MCSubtargetInfo> X(TheX86_32Target);<br>
- RegisterMCSubtargetInfo<MCSubtargetInfo> Y(TheX86_64Target);<br>
-<br>
- TargetRegistry::RegisterMCSubtargetInfo(TheX86_32Target,<br>
- createX86MCSubtargetInfo);<br>
- TargetRegistry::RegisterMCSubtargetInfo(TheX86_64Target,<br>
- createX86MCSubtargetInfo);<br>
-}<br>
<br>
Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h?rev=134678&r1=134677&r2=134678&view=diff" target="_blank" class="cremed">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h?rev=134678&r1=134677&r2=134678&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h (original)<br>
+++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h Thu Jul 7 20:53:10 2011<br>
@@ -17,6 +17,7 @@<br>
#include <string><br>
<br>
namespace llvm {<br>
+class MCSubtargetInfo;<br>
class Target;<br>
class StringRef;<br>
<br>
@@ -31,9 +32,17 @@<br>
unsigned *rEBX, unsigned *rECX, unsigned *rEDX);<br>
<br>
void DetectFamilyModel(unsigned EAX, unsigned &Family, unsigned &Model);<br>
+<br>
+ /// createARMMCSubtargetInfo - Create a X86 MCSubtargetInfo instance.<br>
+ /// This is exposed so Asm parser, etc. do not need to go through<br>
+ /// TargetRegistry.<br>
+ MCSubtargetInfo *createX86MCSubtargetInfo(StringRef TT, StringRef CPU,<br>
+ StringRef FS);<br>
}<br>
+<br>
} // End llvm namespace<br>
<br>
+<br>
// Defines symbolic names for X86 registers. This defines a mapping from<br>
// register name to register number.<br>
//<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=134678&r1=134677&r2=134678&view=diff" target="_blank" class="cremed">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=134678&r1=134677&r2=134678&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)<br>
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Thu Jul 7 20:53:10 2011<br>
@@ -438,8 +438,10 @@<br>
def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;<br>
def FPStackf32 : Predicate<"!Subtarget->hasXMM()">;<br>
def FPStackf64 : Predicate<"!Subtarget->hasXMMInt()">;<br>
-def In32BitMode : Predicate<"!Subtarget->is64Bit()">, AssemblerPredicate;<br>
-def In64BitMode : Predicate<"Subtarget->is64Bit()">, AssemblerPredicate;<br>
+def In32BitMode : Predicate<"!Subtarget->is64Bit()">,<br>
+ AssemblerPredicate<"!Mode64Bit">;<br>
+def In64BitMode : Predicate<"Subtarget->is64Bit()">,<br>
+ AssemblerPredicate<"Mode64Bit">;<br>
def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;<br>
def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;<br>
def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff" target="_blank" class="cremed">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Thu Jul 7 20:53:10 2011<br>
@@ -21,9 +21,10 @@<br>
#include "llvm/Target/TargetMachine.h"<br>
#include "llvm/ADT/SmallVector.h"<br>
<br>
-#define GET_SUBTARGETINFO_CTOR<br>
+#define GET_SUBTARGETINFO_ENUM<br>
#define GET_SUBTARGETINFO_MC_DESC<br>
#define GET_SUBTARGETINFO_TARGET_DESC<br>
+#define GET_SUBTARGETINFO_CTOR<br>
#include "X86GenSubtargetInfo.inc"<br>
<br>
using namespace llvm;<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff" target="_blank" class="cremed">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Thu Jul 7 20:53:10 2011<br>
@@ -119,7 +119,7 @@<br>
X86TargetMachine::X86TargetMachine(const Target &T, const std::string &TT,<br>
const std::string &CPU,<br>
const std::string &FS, bool is64Bit)<br>
- : LLVMTargetMachine(T, TT),<br>
+ : LLVMTargetMachine(T, TT, CPU, FS),<br>
Subtarget(TT, CPU, FS, StackAlignmentOverride),<br>
FrameLowering(*this, Subtarget),<br>
ELFWriterInfo(is64Bit, true) {<br>
<br>
Modified: llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff" target="_blank" class="cremed">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp?rev=134678&r1=134677&r2=134678&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp (original)<br>
+++ llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp Thu Jul 7 20:53:10 2011<br>
@@ -14,9 +14,10 @@<br>
#include "XCoreSubtarget.h"<br>
#include "XCore.h"<br>
<br>
-#define GET_SUBTARGETINFO_CTOR<br>
+#define GET_SUBTARGETINFO_ENUM<br>
#define GET_SUBTARGETINFO_MC_DESC<br>
#define GET_SUBTARGETINFO_TARGET_DESC<br>
+#define GET_SUBTARGETINFO_CTOR<br>
#include "XCoreGenSubtargetInfo.inc"<br>
<br>
using namespace llvm;<br>
<br>
Modified: llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff" target="_blank" class="cremed">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp?rev=134678&r1=134677&r2=134678&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp (original)<br>
+++ llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp Thu Jul 7 20:53:10 2011<br>
@@ -23,7 +23,7 @@<br>
XCoreTargetMachine::XCoreTargetMachine(const Target &T, const std::string &TT,<br>
const std::string &CPU,<br>
const std::string &FS)<br>
- : LLVMTargetMachine(T, TT),<br>
+ : LLVMTargetMachine(T, TT, CPU, FS),<br>
Subtarget(TT, CPU, FS),<br>
DataLayout("e-p:32:32:32-a0:0:32-f32:32:32-f64:32:32-i1:8:32-i8:8:32-"<br>
"i16:16:32-i32:32:32-i64:32:32-n32"),<br>
<br>
Modified: llvm/trunk/tools/llvm-mc/llvm-mc.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/llvm-mc.cpp?rev=134678&r1=134677&r2=134678&view=diff" target="_blank" class="cremed">http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/llvm-mc.cpp?rev=134678&r1=134677&r2=134678&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/tools/llvm-mc/llvm-mc.cpp (original)<br>
+++ llvm/trunk/tools/llvm-mc/llvm-mc.cpp Thu Jul 7 20:53:10 2011<br>
@@ -371,7 +371,8 @@<br>
<br>
OwningPtr<MCAsmParser> Parser(createMCAsmParser(*TheTarget, SrcMgr, Ctx,<br>
*Str.get(), *MAI));<br>
- OwningPtr<TargetAsmParser> TAP(TheTarget->createAsmParser(*Parser, *TM));<br>
+ OwningPtr<TargetAsmParser><br>
+ TAP(TheTarget->createAsmParser(TripleName, MCPU, FeaturesStr, *Parser));<br>
if (!TAP) {<br>
errs() << ProgName<br>
<< ": error: this target does not support assembly parsing.\n";<br>
<br>
Modified: llvm/trunk/tools/lto/LTOModule.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOModule.cpp?rev=134678&r1=134677&r2=134678&view=diff" target="_blank" class="cremed">http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOModule.cpp?rev=134678&r1=134677&r2=134678&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/tools/lto/LTOModule.cpp (original)<br>
+++ llvm/trunk/tools/lto/LTOModule.cpp Thu Jul 7 20:53:10 2011<br>
@@ -619,7 +619,10 @@<br>
Context, *Streamer,<br>
*_target->getMCAsmInfo()));<br>
OwningPtr<TargetAsmParser><br>
- TAP(_target->getTarget().createAsmParser(*Parser.get(), *_target.get()));<br>
+ TAP(_target->getTarget().createAsmParser(_target->getTargetTriple(),<br>
+ _target->getTargetCPU(),<br>
+ _target->getTargetFeatureString(),<br>
+ *Parser.get()));<br>
Parser->setTargetParser(*TAP);<br>
int Res = Parser->Run(false);<br>
if (Res)<br>
<br>
Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=134678&r1=134677&r2=134678&view=diff" target="_blank" class="cremed">http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=134678&r1=134677&r2=134678&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original)<br>
+++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Thu Jul 7 20:53:10 2011<br>
@@ -1817,15 +1817,43 @@<br>
Info.AsmParser->getValueAsString("AsmParserClassName");<br>
<br>
OS << "unsigned " << Info.Target.getName() << ClassName << "::\n"<br>
- << "ComputeAvailableFeatures(const " << Info.Target.getName()<br>
- << "Subtarget *Subtarget) const {\n";<br>
+ << "ComputeAvailableFeatures(uint64_t FB) const {\n";<br>
OS << " unsigned Features = 0;\n";<br>
for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator<br>
it = Info.SubtargetFeatures.begin(),<br>
ie = Info.SubtargetFeatures.end(); it != ie; ++it) {<br>
SubtargetFeatureInfo &SFI = *it->second;<br>
- OS << " if (" << SFI.TheDef->getValueAsString("CondString")<br>
- << ")\n";<br>
+<br>
+ OS << " if (";<br>
+ StringRef Conds = SFI.TheDef->getValueAsString("AssemblerCondString");<br>
+ std::pair<StringRef,StringRef> Comma = Conds.split(',');<br>
+ bool First = true;<br>
+ do {<br>
+ if (!First)<br>
+ OS << " && ";<br>
+<br>
+ bool Neg = false;<br>
+ StringRef Cond = Comma.first;<br>
+ if (Cond[0] == '!') {<br>
+ Neg = true;<br>
+ Cond = Cond.substr(1);<br>
+ }<br>
+<br>
+ OS << "((FB & " << Info.Target.getName() << "::" << Cond << ")";<br>
+ if (Neg)<br>
+ OS << " == 0";<br>
+ else<br>
+ OS << " != 0";<br>
+ OS << ")";<br>
+<br>
+ if (Comma.second.empty())<br>
+ break;<br>
+<br>
+ First = false;<br>
+ Comma = Comma.second.split(',');<br>
+ } while (true);<br>
+<br>
+ OS << ")\n";<br>
OS << " Features |= " << SFI.getEnumName() << ";\n";<br>
}<br>
OS << " return Features;\n";<br>
@@ -2140,8 +2168,7 @@<br>
OS << "#undef GET_ASSEMBLER_HEADER\n";<br>
OS << " // This should be included into the middle of the declaration of\n";<br>
OS << " // your subclasses implementation of TargetAsmParser.\n";<br>
- OS << " unsigned ComputeAvailableFeatures(const " <<<br>
- Target.getName() << "Subtarget *Subtarget) const;\n";<br>
+ OS << " unsigned ComputeAvailableFeatures(uint64_t FeatureBits) const;\n";<br>
OS << " enum MatchResultTy {\n";<br>
OS << " Match_ConversionFail,\n";<br>
OS << " Match_InvalidOperand,\n";<br>
<br>
Modified: llvm/trunk/utils/TableGen/SubtargetEmitter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/SubtargetEmitter.cpp?rev=134678&r1=134677&r2=134678&view=diff" target="_blank" class="cremed">http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/SubtargetEmitter.cpp?rev=134678&r1=134677&r2=134678&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/utils/TableGen/SubtargetEmitter.cpp (original)<br>
+++ llvm/trunk/utils/TableGen/SubtargetEmitter.cpp Thu Jul 7 20:53:10 2011<br>
@@ -645,12 +645,18 @@<br>
<br>
EmitSourceFileHeader("Subtarget Enumeration Source Fragment", OS);<br>
<br>
+ OS << "\n#ifdef GET_SUBTARGETINFO_ENUM\n";<br>
+ OS << "#undef GET_SUBTARGETINFO_ENUM\n";<br>
+<br>
+ OS << "namespace llvm {\n";<br>
+ Enumeration(OS, "SubtargetFeature", true);<br>
+ OS << "} // End llvm namespace \n";<br>
+ OS << "#endif // GET_SUBTARGETINFO_ENUM\n\n";<br>
+<br>
OS << "\n#ifdef GET_SUBTARGETINFO_MC_DESC\n";<br>
OS << "#undef GET_SUBTARGETINFO_MC_DESC\n";<br>
<br>
OS << "namespace llvm {\n";<br>
- Enumeration(OS, "SubtargetFeature", true);<br>
- OS<<"\n";<br>
unsigned NumFeatures = FeatureKeyValues(OS);<br>
OS<<"\n";<br>
unsigned NumProcs = CPUKeyValues(OS);<br>
<br>
<br>
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