[llvm-commits] Fix sitofp and fpextend codegen for x86/AVX[PR9473]

[Syoyo Fujita]

Attached are series of patch to fix sitofp and fpextend instruction
isel for x86/AVX backend(mattr=+avx).

The problem is reported here

http://lists.cs.uiuc.edu/pipermail/llvmdev/2011-March/038913.html

and in bugzilla PR9473.


Let me briefly explain what this patches do.

sitofp instruction should be mapped to vcvtsitoss(or vcvtsitosd)
assembler, and fpextend should be vcvtss2sd.
These AVX instruction takes 2 input and 1 output in asm form, but for
codegen(isel) form it should be 1 input and 1 output.
It seems impossible to define DUMMY register in .td.

So my solution is to separate .td definition into asm parser
case(isAsmParserOnly=1) and codegen case(isCodeGenOnly =1)

--
Syoyo
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