[llvm-commits] [llvm] r131518 - /llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

[Cameron Zwarich]

Author: zwarich
Date: Tue May 17 21:20:07 2011
New Revision: 131518

URL: http://llvm.org/viewvc/llvm-project?rev=131518&view=rev
Log:
Fix more of PR8825 by correctly using rGPR registers when lowering atomic
compare-and-swap intrinsics.

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=131518&r1=131517&r2=131518&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue May 17 21:20:07 2011
@@ -4860,12 +4860,21 @@
   unsigned ptr     = MI->getOperand(1).getReg();
   unsigned oldval  = MI->getOperand(2).getReg();
   unsigned newval  = MI->getOperand(3).getReg();
-  unsigned scratch = BB->getParent()->getRegInfo()
-    .createVirtualRegister(ARM::GPRRegisterClass);
   const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
   DebugLoc dl = MI->getDebugLoc();
   bool isThumb2 = Subtarget->isThumb2();
 
+  MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
+  unsigned scratch =
+    MRI.createVirtualRegister(isThumb2 ? ARM::tGPRRegisterClass
+                                       : ARM::GPRRegisterClass);
+
+  if (isThumb2) {
+    MRI.constrainRegClass(dest, ARM::tGPRRegisterClass);
+    MRI.constrainRegClass(oldval, ARM::tGPRRegisterClass);
+    MRI.constrainRegClass(newval, ARM::tGPRRegisterClass);
+  }
+
   unsigned ldrOpc, strOpc;
   switch (Size) {
   default: llvm_unreachable("unsupported size for AtomicCmpSwap!");