[llvm-commits] [PATCH] A patch to add vector SHL/SRL/SRA support for x86

[Rotem, Nadav]

Hi Eli, 

Do you suggest that we remove PerformShiftCombine altogether ?  Can you think of a scenario which would require us to have this in the DAGCombining phase ?

Would you oppose keeping both translations if I refactor the code to use the same utility function ?

Thanks,
Nadav


-----Original Message-----
From: Eli Friedman [mailto:eli.friedman at gmail.com] 
Sent: Sunday, May 08, 2011 19:07
To: Rotem, Nadav
Cc: llvm-commits at cs.uiuc.edu
Subject: Re: [llvm-commits] [PATCH] A patch to add vector SHL/SRL/SRA support for x86

On Sun, May 8, 2011 at 6:59 AM, Rotem, Nadav <nadav.rotem at intel.com> wrote:
> Hi Eli,
>
> Thanks for the quick reply. When I worked on implementing the 'vector-select' feature, I found several cases where PerformShiftCombine was unable to convert vector shifts to x86-shifts. Often, the shift amount operand (originally expresses as a BUILD_VECTOR) was already lowered to a constant pool read. This scenario is likely to happen in places where the op legalizer creates new shift instructions. This happened to me when I implemented the operation legalization of vector SIGN_EXTEND_INREG. I assumed that this is a good place to add the vector-shift lowering because this is where vector-SHL was implemented.

I'm not really arguing with the placement; I'm primarily just opposed
to having the same shift-matching code in two places.

-Eli
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