[llvm-commits] [llvm] r127681 - /llvm/trunk/lib/Target/XCore/XCoreISelDAGToDAG.cpp

[Richard Osborne]

Author: friedgold
Date: Tue Mar 15 10:55:30 2011
New Revision: 127681

URL: http://llvm.org/viewvc/llvm-project?rev=127681&view=rev
Log:
Don't indent cases in a switch, no functionality change.

Modified:
    llvm/trunk/lib/Target/XCore/XCoreISelDAGToDAG.cpp

Modified: llvm/trunk/lib/Target/XCore/XCoreISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelDAGToDAG.cpp?rev=127681&r1=127680&r2=127681&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/XCore/XCoreISelDAGToDAG.cpp Tue Mar 15 10:55:30 2011
@@ -157,58 +157,58 @@
   EVT NVT = N->getValueType(0);
   if (NVT == MVT::i32) {
     switch (N->getOpcode()) {
-      default: break;
-      case ISD::Constant: {
-        uint64_t Val = cast<ConstantSDNode>(N)->getZExtValue();
-        if (immMskBitp(N)) {
-          // Transformation function: get the size of a mask
-          // Look for the first non-zero bit
-          SDValue MskSize = getI32Imm(32 - CountLeadingZeros_32(Val));
-          return CurDAG->getMachineNode(XCore::MKMSK_rus, dl,
-                                        MVT::i32, MskSize);
-        }
-        else if (!isUInt<16>(Val)) {
-          SDValue CPIdx =
-            CurDAG->getTargetConstantPool(ConstantInt::get(
-                                  Type::getInt32Ty(*CurDAG->getContext()), Val),
-                                          TLI.getPointerTy());
-          return CurDAG->getMachineNode(XCore::LDWCP_lru6, dl, MVT::i32, 
-                                        MVT::Other, CPIdx, 
-                                        CurDAG->getEntryNode());
-        }
-        break;
+    default: break;
+    case ISD::Constant: {
+      uint64_t Val = cast<ConstantSDNode>(N)->getZExtValue();
+      if (immMskBitp(N)) {
+        // Transformation function: get the size of a mask
+        // Look for the first non-zero bit
+        SDValue MskSize = getI32Imm(32 - CountLeadingZeros_32(Val));
+        return CurDAG->getMachineNode(XCore::MKMSK_rus, dl,
+                                      MVT::i32, MskSize);
+      }
+      else if (!isUInt<16>(Val)) {
+        SDValue CPIdx =
+          CurDAG->getTargetConstantPool(ConstantInt::get(
+                                Type::getInt32Ty(*CurDAG->getContext()), Val),
+                                        TLI.getPointerTy());
+        return CurDAG->getMachineNode(XCore::LDWCP_lru6, dl, MVT::i32, 
+                                      MVT::Other, CPIdx, 
+                                      CurDAG->getEntryNode());
       }
-      case XCoreISD::LADD: {
-        SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
-                            N->getOperand(2) };
-        return CurDAG->getMachineNode(XCore::LADD_l5r, dl, MVT::i32, MVT::i32,
-                                      Ops, 3);
-      }
-      case XCoreISD::LSUB: {
-        SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
-                            N->getOperand(2) };
-        return CurDAG->getMachineNode(XCore::LSUB_l5r, dl, MVT::i32, MVT::i32,
-                                      Ops, 3);
-      }
-      case XCoreISD::MACCU: {
-        SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
-                          N->getOperand(2), N->getOperand(3) };
-        return CurDAG->getMachineNode(XCore::MACCU_l4r, dl, MVT::i32, MVT::i32,
-                                      Ops, 4);
-      }
-      case XCoreISD::MACCS: {
-        SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
-                          N->getOperand(2), N->getOperand(3) };
-        return CurDAG->getMachineNode(XCore::MACCS_l4r, dl, MVT::i32, MVT::i32,
-                                      Ops, 4);
-      }
-      case XCoreISD::LMUL: {
-        SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
-                          N->getOperand(2), N->getOperand(3) };
-        return CurDAG->getMachineNode(XCore::LMUL_l6r, dl, MVT::i32, MVT::i32,
-                                      Ops, 4);
-      }
-      // Other cases are autogenerated.
+      break;
+    }
+    case XCoreISD::LADD: {
+      SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
+                          N->getOperand(2) };
+      return CurDAG->getMachineNode(XCore::LADD_l5r, dl, MVT::i32, MVT::i32,
+                                    Ops, 3);
+    }
+    case XCoreISD::LSUB: {
+      SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
+                          N->getOperand(2) };
+      return CurDAG->getMachineNode(XCore::LSUB_l5r, dl, MVT::i32, MVT::i32,
+                                    Ops, 3);
+    }
+    case XCoreISD::MACCU: {
+      SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
+                        N->getOperand(2), N->getOperand(3) };
+      return CurDAG->getMachineNode(XCore::MACCU_l4r, dl, MVT::i32, MVT::i32,
+                                    Ops, 4);
+    }
+    case XCoreISD::MACCS: {
+      SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
+                        N->getOperand(2), N->getOperand(3) };
+      return CurDAG->getMachineNode(XCore::MACCS_l4r, dl, MVT::i32, MVT::i32,
+                                    Ops, 4);
+    }
+    case XCoreISD::LMUL: {
+      SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
+                        N->getOperand(2), N->getOperand(3) };
+      return CurDAG->getMachineNode(XCore::LMUL_l6r, dl, MVT::i32, MVT::i32,
+                                    Ops, 4);
+    }
+    // Other cases are autogenerated.
     }
   }
   return SelectCode(N);