[llvm-commits] [llvm] r124910 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Nick Lewycky
nlewycky at google.com
Fri Feb 4 16:07:20 PST 2011
Hi David, you broke our build:
llvm/lib/Target/X86/X86ISelLowering.cpp:78: error: 'llvm::SDValue
Extract128BitVector(llvm::SDValue, llvm::SDValue, llvm::SelectionDAG&,
llvm::DebugLoc)' defined but not used [-Wunused-function]
llvm/lib/Target/X86/X86ISelLowering.cpp:157: error: 'llvm::SDValue
ConcatVectors(llvm::SDValue, llvm::SDValue, llvm::SelectionDAG&)' defined
but not used [-Wunused-function] llvm/lib/Target/X86/X86ISelLowering.cpp:78:
error: 'llvm::SDValue Extract128BitVector(llvm::SDValue, llvm::SDValue,
llvm::SelectionDAG&, llvm::DebugLoc)' defined but not used
[-Wunused-function]
llvm/lib/Target/X86/X86ISelLowering.cpp:157: error: 'llvm::SDValue
ConcatVectors(llvm::SDValue, llvm::SDValue, llvm::SelectionDAG&)' defined
but not used [-Wunused-function]
Yup, we use -Werror. Are you going to commit the patch that makes use of
these functions soon?
Nick
On 4 February 2011 15:29, David Greene <greened at obbligato.org> wrote:
> Author: greened
> Date: Fri Feb 4 17:29:33 2011
> New Revision: 124910
>
> URL: http://llvm.org/viewvc/llvm-project?rev=124910&view=rev
> Log:
>
> [AVX] Add some utilities to insert and extract 128-bit subvectors.
> This allows us to easily support 256-bit operations that don't have
> native 256-bit support. This applies to integer operations, certain
> types of shuffles and various othher things.
>
> Modified:
> llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=124910&r1=124909&r2=124910&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Feb 4 17:29:33 2011
> @@ -60,6 +60,128 @@
> static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
> SDValue V2);
>
> +static SDValue Insert128BitVector(SDValue Result,
> + SDValue Vec,
> + SDValue Idx,
> + SelectionDAG &DAG,
> + DebugLoc dl);
> +static SDValue Extract128BitVector(SDValue Vec,
> + SDValue Idx,
> + SelectionDAG &DAG,
> + DebugLoc dl);
> +
> +static SDValue ConcatVectors(SDValue Lower, SDValue Upper, SelectionDAG
> &DAG);
> +
> +/// Generate a DAG to grab 128-bits from a vector > 128 bits. This
> +/// sets things up to match to an AVX VEXTRACTF128 instruction or a
> +/// simple subregister reference.
> +static SDValue Extract128BitVector(SDValue Vec,
> + SDValue Idx,
> + SelectionDAG &DAG,
> + DebugLoc dl) {
> + EVT VT = Vec.getValueType();
> + assert(VT.getSizeInBits() == 256 && "Unexpected vector size!");
> +
> + EVT ElVT = VT.getVectorElementType();
> +
> + int Factor = VT.getSizeInBits() / 128;
> +
> + EVT ResultVT = EVT::getVectorVT(*DAG.getContext(),
> + ElVT,
> + VT.getVectorNumElements() / Factor);
> +
> + // Extract from UNDEF is UNDEF.
> + if (Vec.getOpcode() == ISD::UNDEF)
> + return DAG.getNode(ISD::UNDEF, dl, ResultVT);
> +
> + if (isa<ConstantSDNode>(Idx)) {
> + unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
> +
> + // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
> + // we can match to VEXTRACTF128.
> + unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
> +
> + // This is the index of the first element of the 128-bit chunk
> + // we want.
> + unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
> + * ElemsPerChunk);
> +
> + SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
> +
> + SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT,
> Vec,
> + VecIdx);
> +
> + return Result;
> + }
> +
> + return SDValue();
> +}
> +
> +/// Generate a DAG to put 128-bits into a vector > 128 bits. This
> +/// sets things up to match to an AVX VINSERTF128 instruction or a
> +/// simple superregister reference.
> +static SDValue Insert128BitVector(SDValue Result,
> + SDValue Vec,
> + SDValue Idx,
> + SelectionDAG &DAG,
> + DebugLoc dl) {
> + if (isa<ConstantSDNode>(Idx)) {
> + EVT VT = Vec.getValueType();
> + assert(VT.getSizeInBits() == 128 && "Unexpected vector size!");
> +
> + EVT ElVT = VT.getVectorElementType();
> +
> + unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
> +
> + EVT ResultVT = Result.getValueType();
> +
> + // Insert the relevant 128 bits.
> + unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
> +
> + // This is the index of the first element of the 128-bit chunk
> + // we want.
> + unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
> + * ElemsPerChunk);
> +
> + SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
> +
> + Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
> + VecIdx);
> + return Result;
> + }
> +
> + return SDValue();
> +}
> +
> +/// Given two vectors, concat them.
> +static SDValue ConcatVectors(SDValue Lower, SDValue Upper, SelectionDAG
> &DAG) {
> + DebugLoc dl = Lower.getDebugLoc();
> +
> + assert(Lower.getValueType() == Upper.getValueType() && "Mismatched
> vectors!");
> +
> + EVT VT = EVT::getVectorVT(*DAG.getContext(),
> + Lower.getValueType().getVectorElementType(),
> + Lower.getValueType().getVectorNumElements() *
> 2);
> +
> + // TODO: Generalize to arbitrary vector length (this assumes 256-bit
> vectors).
> + assert(VT.getSizeInBits() == 256 && "Unsupported vector concat!");
> +
> + // Insert the upper subvector.
> + SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Upper,
> + DAG.getConstant(
> + // This is half the length of the
> result
> + // vector. Start inserting the upper
> 128
> + // bits here.
> + Lower.getValueType().
> + getVectorNumElements(),
> + MVT::i32),
> + DAG, dl);
> +
> + // Insert the lower subvector.
> + Vec = Insert128BitVector(Vec, Lower, DAG.getConstant(0, MVT::i32), DAG,
> dl);
> + return Vec;
> +}
> +
> static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
> const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
> bool is64Bit = Subtarget->is64Bit();
>
>
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