<meta http-equiv="content-type" content="text/html; charset=utf-8"><div>Hi David, you broke our build:</div><div><br></div>llvm/lib/Target/X86/X86ISelLowering.cpp:78: error: 'llvm::SDValue Extract128BitVector(llvm::SDValue, llvm::SDValue, llvm::SelectionDAG&, llvm::DebugLoc)' defined but not used [-Wunused-function]<div>
llvm/lib/Target/X86/X86ISelLowering.cpp:157: error: 'llvm::SDValue ConcatVectors(llvm::SDValue, llvm::SDValue, llvm::SelectionDAG&)' defined but not used [-Wunused-function] llvm/lib/Target/X86/X86ISelLowering.cpp:78: error: 'llvm::SDValue Extract128BitVector(llvm::SDValue, llvm::SDValue, llvm::SelectionDAG&, llvm::DebugLoc)' defined but not used [-Wunused-function]</div>
<div>llvm/lib/Target/X86/X86ISelLowering.cpp:157: error: 'llvm::SDValue ConcatVectors(llvm::SDValue, llvm::SDValue, llvm::SelectionDAG&)' defined but not used [-Wunused-function]</div><div><br></div><div>Yup, we use -Werror. Are you going to commit the patch that makes use of these functions soon?</div>
<div><br></div><div>Nick</div><div><br></div><div><div class="gmail_quote">On 4 February 2011 15:29, David Greene <span dir="ltr"><<a href="mailto:greened@obbligato.org">greened@obbligato.org</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex;">
Author: greened<br>
Date: Fri Feb 4 17:29:33 2011<br>
New Revision: 124910<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=124910&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=124910&view=rev</a><br>
Log:<br>
<br>
[AVX] Add some utilities to insert and extract 128-bit subvectors.<br>
This allows us to easily support 256-bit operations that don't have<br>
native 256-bit support. This applies to integer operations, certain<br>
types of shuffles and various othher things.<br>
<br>
Modified:<br>
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=124910&r1=124909&r2=124910&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=124910&r1=124909&r2=124910&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Feb 4 17:29:33 2011<br>
@@ -60,6 +60,128 @@<br>
static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,<br>
SDValue V2);<br>
<br>
+static SDValue Insert128BitVector(SDValue Result,<br>
+ SDValue Vec,<br>
+ SDValue Idx,<br>
+ SelectionDAG &DAG,<br>
+ DebugLoc dl);<br>
+static SDValue Extract128BitVector(SDValue Vec,<br>
+ SDValue Idx,<br>
+ SelectionDAG &DAG,<br>
+ DebugLoc dl);<br>
+<br>
+static SDValue ConcatVectors(SDValue Lower, SDValue Upper, SelectionDAG &DAG);<br>
+<br>
+/// Generate a DAG to grab 128-bits from a vector > 128 bits. This<br>
+/// sets things up to match to an AVX VEXTRACTF128 instruction or a<br>
+/// simple subregister reference.<br>
+static SDValue Extract128BitVector(SDValue Vec,<br>
+ SDValue Idx,<br>
+ SelectionDAG &DAG,<br>
+ DebugLoc dl) {<br>
+ EVT VT = Vec.getValueType();<br>
+ assert(VT.getSizeInBits() == 256 && "Unexpected vector size!");<br>
+<br>
+ EVT ElVT = VT.getVectorElementType();<br>
+<br>
+ int Factor = VT.getSizeInBits() / 128;<br>
+<br>
+ EVT ResultVT = EVT::getVectorVT(*DAG.getContext(),<br>
+ ElVT,<br>
+ VT.getVectorNumElements() / Factor);<br>
+<br>
+ // Extract from UNDEF is UNDEF.<br>
+ if (Vec.getOpcode() == ISD::UNDEF)<br>
+ return DAG.getNode(ISD::UNDEF, dl, ResultVT);<br>
+<br>
+ if (isa<ConstantSDNode>(Idx)) {<br>
+ unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();<br>
+<br>
+ // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR<br>
+ // we can match to VEXTRACTF128.<br>
+ unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();<br>
+<br>
+ // This is the index of the first element of the 128-bit chunk<br>
+ // we want.<br>
+ unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)<br>
+ * ElemsPerChunk);<br>
+<br>
+ SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);<br>
+<br>
+ SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,<br>
+ VecIdx);<br>
+<br>
+ return Result;<br>
+ }<br>
+<br>
+ return SDValue();<br>
+}<br>
+<br>
+/// Generate a DAG to put 128-bits into a vector > 128 bits. This<br>
+/// sets things up to match to an AVX VINSERTF128 instruction or a<br>
+/// simple superregister reference.<br>
+static SDValue Insert128BitVector(SDValue Result,<br>
+ SDValue Vec,<br>
+ SDValue Idx,<br>
+ SelectionDAG &DAG,<br>
+ DebugLoc dl) {<br>
+ if (isa<ConstantSDNode>(Idx)) {<br>
+ EVT VT = Vec.getValueType();<br>
+ assert(VT.getSizeInBits() == 128 && "Unexpected vector size!");<br>
+<br>
+ EVT ElVT = VT.getVectorElementType();<br>
+<br>
+ unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();<br>
+<br>
+ EVT ResultVT = Result.getValueType();<br>
+<br>
+ // Insert the relevant 128 bits.<br>
+ unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();<br>
+<br>
+ // This is the index of the first element of the 128-bit chunk<br>
+ // we want.<br>
+ unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)<br>
+ * ElemsPerChunk);<br>
+<br>
+ SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);<br>
+<br>
+ Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,<br>
+ VecIdx);<br>
+ return Result;<br>
+ }<br>
+<br>
+ return SDValue();<br>
+}<br>
+<br>
+/// Given two vectors, concat them.<br>
+static SDValue ConcatVectors(SDValue Lower, SDValue Upper, SelectionDAG &DAG) {<br>
+ DebugLoc dl = Lower.getDebugLoc();<br>
+<br>
+ assert(Lower.getValueType() == Upper.getValueType() && "Mismatched vectors!");<br>
+<br>
+ EVT VT = EVT::getVectorVT(*DAG.getContext(),<br>
+ Lower.getValueType().getVectorElementType(),<br>
+ Lower.getValueType().getVectorNumElements() * 2);<br>
+<br>
+ // TODO: Generalize to arbitrary vector length (this assumes 256-bit vectors).<br>
+ assert(VT.getSizeInBits() == 256 && "Unsupported vector concat!");<br>
+<br>
+ // Insert the upper subvector.<br>
+ SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Upper,<br>
+ DAG.getConstant(<br>
+ // This is half the length of the result<br>
+ // vector. Start inserting the upper 128<br>
+ // bits here.<br>
+ Lower.getValueType().<br>
+ getVectorNumElements(),<br>
+ MVT::i32),<br>
+ DAG, dl);<br>
+<br>
+ // Insert the lower subvector.<br>
+ Vec = Insert128BitVector(Vec, Lower, DAG.getConstant(0, MVT::i32), DAG, dl);<br>
+ return Vec;<br>
+}<br>
+<br>
static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {<br>
const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();<br>
bool is64Bit = Subtarget->is64Bit();<br>
<br>
<br>
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</blockquote></div><br></div>