[llvm-commits] [llvm] r122354 - in /llvm/trunk: lib/CodeGen/SelectionDAG/DAGCombiner.cpp test/CodeGen/X86/divide-by-constant.ll

[Dale Johannesen]

Author: johannes
Date: Tue Dec 21 14:06:19 2010
New Revision: 122354

URL: http://llvm.org/viewvc/llvm-project?rev=122354&view=rev
Log:
Get the type of a shift from the shift, not from its shift
count operand.  These should be the same but apparently are
not always, and this is cleaner anyway.  This improves the
code in an existing test.


Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/test/CodeGen/X86/divide-by-constant.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=122354&r1=122353&r2=122354&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Dec 21 14:06:19 2010
@@ -3178,7 +3178,7 @@
     uint64_t c1 = 
       cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
     uint64_t c2 = N1C->getZExtValue();
-    EVT InnerShiftVT = N0.getOperand(0)->getOperand(1).getValueType();
+    EVT InnerShiftVT = N0.getOperand(0).getValueType();
     uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits();
     // This is only valid if the OpSizeInBits + c1 = size of inner shift.
     if (c1 + OpSizeInBits == InnerShiftSize) {

Modified: llvm/trunk/test/CodeGen/X86/divide-by-constant.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/divide-by-constant.ll?rev=122354&r1=122353&r2=122354&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/divide-by-constant.ll (original)
+++ llvm/trunk/test/CodeGen/X86/divide-by-constant.ll Tue Dec 21 14:06:19 2010
@@ -29,9 +29,9 @@
   ret i8 %div
 
 ; CHECK: test3:
-; CHECK: imull	$171, %eax, %eax
-; CHECK-NEXT: shrb	%ah
-; CHECK-NEXT: movzbl	%ah, %eax
+; CHECK: movzbl  8(%esp), %eax
+; CHECK-NEXT: imull	$171, %eax, %eax
+; CHECK-NEXT: shrl	$9, %eax
 ; CHECK-NEXT: ret
 }