[llvm-commits] [llvm] r119307 - in /llvm/trunk/lib/Target/PowerPC: PPCCodeEmitter.cpp PPCMCCodeEmitter.cpp

[Chris Lattner]

Author: lattner
Date: Mon Nov 15 18:55:51 2010
New Revision: 119307

URL: http://llvm.org/viewvc/llvm-project?rev=119307&view=rev
Log:
relax an assertion a bit, allowing the GPR argument of
these instructions to be encoded with getMachineOpValue.
This unbreaks ExecutionEngine/2003-01-04-ArgumentBug.ll 
when running on a G5

Modified:
    llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp
    llvm/trunk/lib/Target/PowerPC/PPCMCCodeEmitter.cpp

Modified: llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp?rev=119307&r1=119306&r2=119307&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp Mon Nov 15 18:55:51 2010
@@ -246,7 +246,10 @@
                                            const MachineOperand &MO) const {
 
   if (MO.isReg()) {
-    assert(MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MFOCRF);
+    // MTCRF/MFOCRF should go through get_crbitm_encoding for the CR operand.
+    // The GPR operand should come through here though.
+    assert((MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MFOCRF) ||
+           MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
     return PPCRegisterInfo::getRegisterNumbering(MO.getReg());
   }
   

Modified: llvm/trunk/lib/Target/PowerPC/PPCMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCMCCodeEmitter.cpp?rev=119307&r1=119306&r2=119307&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCMCCodeEmitter.cpp Mon Nov 15 18:55:51 2010
@@ -199,7 +199,8 @@
 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
                   SmallVectorImpl<MCFixup> &Fixups) const {
   if (MO.isReg()) {
-    assert(MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MFOCRF);
+    assert((MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MFOCRF) ||
+           MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
     return PPCRegisterInfo::getRegisterNumbering(MO.getReg());
   }