[llvm-commits] [llvm] r118469 - in /llvm/trunk/lib/Target/ARM: ARMAsmBackend.cpp ARMMCCodeEmitter.cpp
Jim Grosbach
grosbach at apple.com
Mon Nov 8 17:37:16 PST 2010
Author: grosbach
Date: Mon Nov 8 19:37:15 2010
New Revision: 118469
URL: http://llvm.org/viewvc/llvm-project?rev=118469&view=rev
Log:
Add support for a few simple fixups to the ARM Darwin asm backend. This allows
constant pool references and global variable refernces to resolve properly
for object file generation. For example,
int x;
void foo(unsigned a, unsigned *p) {
p[a] = x;
}
can now be successfully compiled directly to an (ARM mode) object file.
Modified:
llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
Modified: llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp?rev=118469&r1=118468&r2=118469&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp Mon Nov 8 19:37:15 2010
@@ -9,7 +9,7 @@
#include "llvm/Target/TargetAsmBackend.h"
#include "ARM.h"
-//FIXME: add #include "ARMFixupKinds.h"
+#include "ARMFixupKinds.h"
#include "llvm/ADT/Twine.h"
#include "llvm/MC/ELFObjectWriter.h"
#include "llvm/MC/MCAssembler.h"
@@ -138,9 +138,41 @@
}
};
+static unsigned getFixupKindLog2Size(unsigned Kind) {
+ switch (Kind) {
+ default: llvm_unreachable("Unknown fixup kind!");
+ case FK_Data_4: return 2;
+ case ARM::fixup_arm_pcrel_12: return 2;
+ case ARM::fixup_arm_vfp_pcrel_12: return 1;
+ }
+}
+
+static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
+ switch (Kind) {
+ default:
+ llvm_unreachable("Unknown fixup kind!");
+ case FK_Data_4:
+ case ARM::fixup_arm_pcrel_12:
+ // ARM PC-relative values are offset by 8.
+ return Value - 8;
+ case ARM::fixup_arm_vfp_pcrel_12:
+ // The VFP ld/st immediate value doesn't encode the low two bits since
+ // they're always zero. Offset by 8 just as above.
+ return (Value - 8) >> 2;
+ }
+}
+
void DarwinARMAsmBackend::ApplyFixup(const MCFixup &Fixup, MCDataFragment &DF,
uint64_t Value) const {
- assert(0 && "DarwinARMAsmBackend::ApplyFixup() unimplemented");
+ unsigned NumBytes = getFixupKindLog2Size(Fixup.getKind());
+ Value = adjustFixupValue(Fixup.getKind(), Value);
+
+ assert(Fixup.getOffset() + NumBytes <= DF.getContents().size() &&
+ "Invalid fixup offset!");
+ // For each byte of the fragment that the fixup touches, mask in the
+ // bits from the fixup value.
+ for (unsigned i = 0; i != NumBytes; ++i)
+ DF.getContents()[Fixup.getOffset() + i] |= uint8_t(Value >> (i * 8));
}
} // end anonymous namespace
Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=118469&r1=118468&r2=118469&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Mon Nov 8 19:37:15 2010
@@ -234,7 +234,7 @@
// If The first operand isn't a register, we have a label reference.
const MCOperand &MO = MI.getOperand(OpIdx);
if (!MO.isReg()) {
- Reg = ARM::PC; // Rn is PC.
+ Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
Imm12 = 0;
assert(MO.isExpr() && "Unexpected machine operand type!");
@@ -246,9 +246,6 @@
} else
isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups);
- if (Reg == ARM::PC)
- return ARM::PC << 13; // Rn is PC;
-
uint32_t Binary = Imm12 & 0xfff;
// Immediate is always encoded as positive. The 'U' bit controls add vs sub.
if (isAdd)
@@ -268,7 +265,7 @@
// If The first operand isn't a register, we have a label reference.
const MCOperand &MO = MI.getOperand(OpIdx);
if (!MO.isReg()) {
- Reg = ARM::PC; // Rn is PC.
+ Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
Imm8 = 0;
assert(MO.isExpr() && "Unexpected machine operand type!");
@@ -280,9 +277,6 @@
} else
EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
- if (Reg == ARM::PC)
- return ARM::PC << 9; // Rn is PC;
-
uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
// Immediate is always encoded as positive. The 'U' bit controls add vs sub.
if (ARM_AM::getAM5Op(Imm8) == ARM_AM::add)
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