[llvm-commits] [llvm] r117421 - /llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp

[Jim Grosbach]

Author: grosbach
Date: Tue Oct 26 19:38:16 2010
New Revision: 117421

URL: http://llvm.org/viewvc/llvm-project?rev=117421&view=rev
Log:
One more spot where the new arm mode LDR instruction representation
doesn't need the additional addrmode2 register operand. Missed it the first
time around.

Modified:
    llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp?rev=117421&r1=117420&r2=117421&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Tue Oct 26 19:38:16 2010
@@ -860,7 +860,9 @@
                           ARMCC::CondCodes Pred, unsigned PredReg,
                           const TargetInstrInfo *TII, bool isT2) {
   int Offset = OffImm;
-  if (!isT2) {
+  // FIXME: This fancy offset encoding stuff goes away when we're done
+  // removing addrmode2.
+  if (!isT2 && !isDef) {
     if (OffImm < 0)
       Offset = ARM_AM::getAM2Opc(ARM_AM::sub, -OffImm, ARM_AM::no_shift);
     else
@@ -871,8 +873,6 @@
                                       TII->get(NewOpc))
       .addReg(Reg, getDefRegState(true) | getDeadRegState(RegDeadKill))
       .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));
-    if (!isT2)
-      MIB.addReg(OffReg,  getKillRegState(OffKill)|getUndefRegState(OffUndef));
     MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
   } else {
     MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MBBI->getDebugLoc(),