[llvm-commits] [llvm] r116563 - in /llvm/trunk: lib/Target/ARM/ARMInstrFormats.td test/CodeGen/ARM/arm-and-tst-peephole.ll test/MC/Disassembler/arm-tests.txt

[Bob Wilson]

Author: bwilson
Date: Thu Oct 14 22:23:44 2010
New Revision: 116563

URL: http://llvm.org/viewvc/llvm-project?rev=116563&view=rev
Log:
ARM instructions that are both predicated and set the condition codes
have been printed with the "S" modifier after the predicate.  With ARM's
unified syntax, they are supposed to go in the other order.  We fixed this
for Thumb when we switched to unified syntax but missed changing it for
ARM.  Apparently we don't generate these instructions often because no one
noticed until now.  Thanks to Bill Wendling for the testcase!

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
    llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll
    llvm/trunk/test/MC/Disassembler/arm-tests.txt

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=116563&r1=116562&r2=116563&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Thu Oct 14 22:23:44 2010
@@ -284,7 +284,7 @@
 
   let OutOperandList = oops;
   let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
-  let AsmString = !strconcat(opc, "${p}${s}", asm);
+  let AsmString = !strconcat(opc, "${s}${p}", asm);
   let Pattern = pattern;
   list<Predicate> Predicates = [IsARM];
 }

Modified: llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll?rev=116563&r1=116562&r2=116563&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll Thu Oct 14 22:23:44 2010
@@ -59,3 +59,50 @@
 sw.epilog:                                        ; preds = %tailrecurse.switch
   ret %struct.Foo* undef
 }
+
+; Another test that exercises the AND/TST peephole optimization and also
+; generates a predicated ANDS instruction. Check that the predicate is printed
+; after the "S" modifier on the instruction.
+
+%struct.S = type { i8* (i8*)*, [1 x i8] }
+
+; CHECK: bar
+; THUMB: bar
+; T2: bar
+define internal zeroext i8 @bar(%struct.S* %x, %struct.S* nocapture %y) nounwind readonly {
+entry:
+  %0 = getelementptr inbounds %struct.S* %x, i32 0, i32 1, i32 0
+  %1 = load i8* %0, align 1
+  %2 = zext i8 %1 to i32
+; CHECK: ands
+; THUMB: ands
+; T2: ands
+  %3 = and i32 %2, 112
+  %4 = icmp eq i32 %3, 0
+  br i1 %4, label %return, label %bb
+
+bb:                                               ; preds = %entry
+  %5 = getelementptr inbounds %struct.S* %y, i32 0, i32 1, i32 0
+  %6 = load i8* %5, align 1
+  %7 = zext i8 %6 to i32
+; CHECK: andsne
+; THUMB: ands
+; T2: andsne
+  %8 = and i32 %7, 112
+  %9 = icmp eq i32 %8, 0
+  br i1 %9, label %return, label %bb2
+
+bb2:                                              ; preds = %bb
+  %10 = icmp eq i32 %3, 16
+  %11 = icmp eq i32 %8, 16
+  %or.cond = or i1 %10, %11
+  br i1 %or.cond, label %bb4, label %return
+
+bb4:                                              ; preds = %bb2
+  %12 = ptrtoint %struct.S* %x to i32
+  %phitmp = trunc i32 %12 to i8
+  ret i8 %phitmp
+
+return:                                           ; preds = %bb2, %bb, %entry
+  ret i8 1
+}

Modified: llvm/trunk/test/MC/Disassembler/arm-tests.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/arm-tests.txt?rev=116563&r1=116562&r2=116563&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/arm-tests.txt (original)
+++ llvm/trunk/test/MC/Disassembler/arm-tests.txt Thu Oct 14 22:23:44 2010
@@ -51,7 +51,7 @@
 # CHECK:	movt	r8, #65535
 0xff 0x8f 0x4f 0xe3
 
-# CHECK:	mvnpls	r7, #245, 2
+# CHECK:	mvnspl	r7, #245, 2
 0xf5 0x71 0xf0 0x53
 
 # CHECK-NOT:	orr	r7, r8, r7, rrx #0
@@ -81,8 +81,8 @@
 # CHECK:	rsbeq	r0, r2, r0
 0x00 0x00 0x62 0x00
 
-# CHECK-NOT:	rsceqs	r0, r0, r1, lsl #0
-# CHECK:	rsceqs	r0, r0, r1
+# CHECK-NOT:	rscseq	r0, r0, r1, lsl #0
+# CHECK:	rscseq	r0, r0, r1
 0x01 0x00 0xf0 0x00
 
 # CHECK:	sbcs	r0, pc, #1