[llvm-commits] [llvm] r116560 - /llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

[Jim Grosbach]

Author: grosbach
Date: Thu Oct 14 21:29:58 2010
New Revision: 116560

URL: http://llvm.org/viewvc/llvm-project?rev=116560&view=rev
Log:
Encoding info for extension instructions.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=116560&r1=116559&r2=116560&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Oct 14 21:29:58 2010
@@ -614,6 +614,10 @@
                  IIC_iEXTr, opc, "\t$Rd, $Rm",
                  [(set GPR:$Rd, (opnode GPR:$Rm))]>,
               Requires<[IsARM, HasV6]> {
+    bits<4> Rd;
+    bits<4> Rm;
+    let Inst{15-12} = Rd;
+    let Inst{3-0}   = Rm;
     let Inst{11-10} = 0b00;
     let Inst{19-16} = 0b1111;
   }
@@ -621,8 +625,12 @@
                  IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
                  [(set GPR:$Rd, (opnode (rotr GPR:$Rm, rot_imm:$rot)))]>,
               Requires<[IsARM, HasV6]> {
+    bits<4> Rd;
+    bits<4> Rm;
     bits<2> rot;
+    let Inst{15-12} = Rd;
     let Inst{11-10} = rot;
+    let Inst{3-0}   = Rm;
     let Inst{19-16} = 0b1111;
   }
 }