[llvm-commits] [llvm] r113670 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/PeepholeOptimizer.cpp lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseInstrInfo.h
Gabor Greif
ggreif at gmail.com
Mon Sep 13 08:06:29 PDT 2010
On Sep 13, 12:06 pm, Gabor Greif <ggr... at gmail.com> wrote:
> On Sep 12, 2:22 am, Bill Wendling <wendl... at apple.com> wrote:
>
>
>
> > On Sep 11, 2010, at 12:49 AM, Gabor Greif wrote:
>
> > > Bill,
>
[snippery]
>
> Basically separating out the zero leg from the switch to a place where
> the peephole optimizer is more likely to find it. The ARM patch is an
> experiment to teach the ARM-peephole optimizer to take advantage of
> the hint that the zero-leg is hoisted out. This does not work yet
> because of a (suspected by me) bug, where the ARM::ANDri instruction
> seems to be dead. It definitely should not be dead. I am investigating
> the issue. But I would welcome help why that ANDri is appearing
> dead :-)
Sorry for following myself up!
Mystery solved, here the MC output:
ldr r12, [r2, #-4]
and lr, r12, #3
tst r12, #3
beq LBB0_4
@ BB#2: @ %tailrecurse.switch
@ in Loop: Header=BB0_1
Depth=1
cmp lr, #3
moveq r0, r2
ldmiaeq sp!, {r7, pc}
cmp lr, #2
beq LBB0_5
@ BB#3: @ %tailrecurse.switch
The "tst r12, #3" can be replaced here with "cmp lr, #0", because
it is a mask operation testing against 0. We get this:
ldr r12, [r2, #-4]
and lr, r12, #3
cmp lr, #0
beq LBB0_4
@ BB#2: @ %tailrecurse.switch
Now the peephole can apply:
ldr r12, [r2, #-4]
andS lr, r12, #3
beq LBB0_4
effectively choosing the recording variant of AND and eliding the CMP
(formerly known as TST).
Now I can go over your patch and see whether you already implement
this peephole transformation. If not, I'll try to improve on it.
Cheers, and sorry for the confusion,
Gabor
>
> Cheers,
>
> Gabor
>
> > -bw
>
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