[llvm-commits] [llvm] r110762 - /llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp

[Bill Wendling]

Author: void
Date: Tue Aug 10 19:23:00 2010
New Revision: 110762

URL: http://llvm.org/viewvc/llvm-project?rev=110762&view=rev
Log:
Handle ARM compares as well as converting for ARM adds, subs, and thumb2's adds.

Modified:
    llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=110762&r1=110761&r2=110762&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Tue Aug 10 19:23:00 2010
@@ -1358,6 +1358,8 @@
 AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, int &CmpValue) const {
   switch (MI->getOpcode()) {
   default: break;
+  case ARM::CMPri:
+  case ARM::CMPzri:
   case ARM::t2CMPri:
   case ARM::t2CMPzri:
     SrcReg = MI->getOperand(0).getReg();
@@ -1398,6 +1400,9 @@
   // Set the "zero" bit in CPSR.
   switch (MI->getOpcode()) {
   default: break;
+  case ARM::ADDri:
+  case ARM::SUBri:
+  case ARM::t2ADDri:
   case ARM::t2SUBri: {
     MI->RemoveOperand(5);
     MachineInstrBuilder MB(MI);