[llvm-commits] [llvm] r108567 - in /llvm/trunk: docs/ include/llvm/Target/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/Blackfin/ lib/Target/CellSPU/ lib/Target/MBlaze/ lib/Target/MSP430/ lib/Target/Mips/ lib/Target/PIC16/ lib/Target/PowerPC/ lib
Rafael Espindola
espindola at google.com
Sat Jul 17 14:06:11 PDT 2010
Thanks!
On Jul 16, 2010 6:38 PM, "Jakob Stoklund Olesen" <stoklund at 2pi.dk> wrote:
> Author: stoklund
> Date: Fri Jul 16 17:35:46 2010
> New Revision: 108567
>
> URL: http://llvm.org/viewvc/llvm-project?rev=108567&view=rev
> Log:
> Remove the isMoveInstr() hook.
>
> Modified:
> llvm/trunk/docs/WritingAnLLVMBackend.html
> llvm/trunk/include/llvm/Target/TargetInstrInfo.h
> llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
> llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h
> llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp
> llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h
> llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.cpp
> llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.h
> llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp
> llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h
> llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.cpp
> llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.h
> llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp
> llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.h
> llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp
> llvm/trunk/lib/Target/Mips/MipsInstrInfo.h
> llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.cpp
> llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.h
> llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
> llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h
> llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp
> llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h
> llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp
> llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h
> llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
> llvm/trunk/lib/Target/X86/X86InstrInfo.h
> llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp
> llvm/trunk/lib/Target/XCore/XCoreInstrInfo.h
>
> Modified: llvm/trunk/docs/WritingAnLLVMBackend.html
> URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/WritingAnLLVMBackend.html?rev=108567&r1=108566&r2=108567&view=diff
>
==============================================================================
> --- llvm/trunk/docs/WritingAnLLVMBackend.html (original)
> +++ llvm/trunk/docs/WritingAnLLVMBackend.html Fri Jul 16 17:35:46 2010
> @@ -1299,9 +1299,6 @@
> </p>
>
> <ul>
> -<li><tt>isMoveInstr</tt> — Return true if the instruction is a
register to
> - register move; false, otherwise.</li>
> -
> <li><tt>isLoadFromStackSlot</tt> — If the specified machine
instruction is
> a direct load from a stack slot, return the register number of the
> destination and the <tt>FrameIndex</tt> of the stack slot.</li>
>
> Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h
> URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff
>
==============================================================================
> --- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original)
> +++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Fri Jul 16 17:35:46
2010
> @@ -92,15 +92,6 @@
> AliasAnalysis *AA) const;
>
> public:
> - /// isMoveInstr - Return true if the instruction is a register to
register
> - /// move and return the source and dest operands and their sub-register
> - /// indices by reference.
> - virtual bool isMoveInstr(const MachineInstr& MI,
> - unsigned& SrcReg, unsigned& DstReg,
> - unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
> - return false;
> - }
> -
> /// isCoalescableExtInstr - Return true if the instruction is a
"coalescable"
> /// extension instruction. That is, it's like a copy where it's legal for
the
> /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this
returns
>
> Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
> URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff
>
==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Fri Jul 16 17:35:46
2010
> @@ -573,48 +573,6 @@
> return 0; // Not reached
> }
>
> -/// Return true if the instruction is a register to register move and
> -/// leave the source and dest operands in the passed parameters.
> -///
> -bool
> -ARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI,
> - unsigned &SrcReg, unsigned &DstReg,
> - unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
> - switch (MI.getOpcode()) {
> - default: break;
> - case ARM::VMOVS:
> - case ARM::VMOVD:
> - case ARM::VMOVDneon:
> - case ARM::VMOVQ:
> - case ARM::VMOVQQ : {
> - SrcReg = MI.getOperand(1).getReg();
> - DstReg = MI.getOperand(0).getReg();
> - SrcSubIdx = MI.getOperand(1).getSubReg();
> - DstSubIdx = MI.getOperand(0).getSubReg();
> - return true;
> - }
> - case ARM::MOVr:
> - case ARM::MOVr_TC:
> - case ARM::tMOVr:
> - case ARM::tMOVgpr2tgpr:
> - case ARM::tMOVtgpr2gpr:
> - case ARM::tMOVgpr2gpr:
> - case ARM::t2MOVr: {
> - assert(MI.getDesc().getNumOperands() >= 2 &&
> - MI.getOperand(0).isReg() &&
> - MI.getOperand(1).isReg() &&
> - "Invalid ARM MOV instruction");
> - SrcReg = MI.getOperand(1).getReg();
> - DstReg = MI.getOperand(0).getReg();
> - SrcSubIdx = MI.getOperand(1).getSubReg();
> - DstSubIdx = MI.getOperand(0).getSubReg();
> - return true;
> - }
> - }
> -
> - return false;
> -}
> -
> unsigned
> ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
> int &FrameIndex) const {
>
> Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h
> URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff
>
==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h (original)
> +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h Fri Jul 16 17:35:46 2010
> @@ -262,12 +262,6 @@
> ///
> virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
>
> - /// Return true if the instruction is a register to register move and
return
> - /// the source and dest operands and their sub-register indices by
reference.
> - virtual bool isMoveInstr(const MachineInstr &MI,
> - unsigned &SrcReg, unsigned &DstReg,
> - unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
> -
> virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
> int &FrameIndex) const;
> virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
>
> Modified: llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp
> URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff
>
==============================================================================
> --- llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp Fri Jul 16 17:35:46
2010
> @@ -27,32 +27,6 @@
> RI(*this) { }
>
>
> -bool AlphaInstrInfo::isMoveInstr(const MachineInstr& MI,
> - unsigned& sourceReg, unsigned& destReg,
> - unsigned& SrcSR, unsigned& DstSR) const {
> - unsigned oc = MI.getOpcode();
> - if (oc == Alpha::BISr ||
> - oc == Alpha::CPYSS ||
> - oc == Alpha::CPYST ||
> - oc == Alpha::CPYSSt ||
> - oc == Alpha::CPYSTs) {
> - // or r1, r2, r2
> - // cpys(s|t) r1 r2 r2
> - assert(MI.getNumOperands() >= 3 &&
> - MI.getOperand(0).isReg() &&
> - MI.getOperand(1).isReg() &&
> - MI.getOperand(2).isReg() &&
> - "invalid Alpha BIS instruction!");
> - if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
> - sourceReg = MI.getOperand(1).getReg();
> - destReg = MI.getOperand(0).getReg();
> - SrcSR = DstSR = 0;
> - return true;
> - }
> - }
> - return false;
> -}
> -
> unsigned
> AlphaInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
> int &FrameIndex) const {
>
> Modified: llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h
> URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff
>
==============================================================================
> --- llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h (original)
> +++ llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h Fri Jul 16 17:35:46 2010
> @@ -30,12 +30,6 @@
> ///
> virtual const AlphaRegisterInfo &getRegisterInfo() const { return RI; }
>
> - /// Return true if the instruction is a register to register move and
return
> - /// the source and dest operands and their sub-register indices by
reference.
> - virtual bool isMoveInstr(const MachineInstr &MI,
> - unsigned &SrcReg, unsigned &DstReg,
> - unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
> -
> virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
> int &FrameIndex) const;
> virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
>
> Modified: llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.cpp
> URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff
>
==============================================================================
> --- llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.cpp Fri Jul 16
17:35:46 2010
> @@ -28,34 +28,6 @@
> RI(ST, *this),
> Subtarget(ST) {}
>
> -/// Return true if the instruction is a register to register move and
> -/// leave the source and dest operands in the passed parameters.
> -bool BlackfinInstrInfo::isMoveInstr(const MachineInstr &MI,
> - unsigned &SrcReg,
> - unsigned &DstReg,
> - unsigned &SrcSR,
> - unsigned &DstSR) const {
> - SrcSR = DstSR = 0; // No sub-registers.
> - switch (MI.getOpcode()) {
> - case BF::MOVE:
> - case BF::MOVE_ncccc:
> - case BF::MOVE_ccncc:
> - case BF::MOVECC_zext:
> - case BF::MOVECC_nz:
> - DstReg = MI.getOperand(0).getReg();
> - SrcReg = MI.getOperand(1).getReg();
> - return true;
> - case BF::SLL16i:
> - if (MI.getOperand(2).getImm()!=0)
> - return false;
> - DstReg = MI.getOperand(0).getReg();
> - SrcReg = MI.getOperand(1).getReg();
> - return true;
> - default:
> - return false;
> - }
> -}
> -
> /// isLoadFromStackSlot - If the specified machine instruction is a direct
> /// load from a stack slot, return the virtual or physical register number
of
> /// the destination along with the FrameIndex of the loaded stack slot. If
>
> Modified: llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.h
> URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff
>
==============================================================================
> --- llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.h (original)
> +++ llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.h Fri Jul 16 17:35:46
2010
> @@ -30,10 +30,6 @@
> /// always be able to get register info as well (through this method).
> virtual const BlackfinRegisterInfo &getRegisterInfo() const { return RI; }
>
> - virtual bool isMoveInstr(const MachineInstr &MI,
> - unsigned &SrcReg, unsigned &DstReg,
> - unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
> -
> virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
> int &FrameIndex) const;
>
>
> Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp
> URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff
>
==============================================================================
> --- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp Fri Jul 16 17:35:46
2010
> @@ -54,148 +54,6 @@
> RI(*TM.getSubtargetImpl(), *this)
> { /* NOP */ }
>
> -bool
> -SPUInstrInfo::isMoveInstr(const MachineInstr& MI,
> - unsigned& sourceReg,
> - unsigned& destReg,
> - unsigned& SrcSR, unsigned& DstSR) const {
> - SrcSR = DstSR = 0; // No sub-registers.
> -
> - switch (MI.getOpcode()) {
> - default:
> - break;
> - case SPU::ORIv4i32:
> - case SPU::ORIr32:
> - case SPU::ORHIv8i16:
> - case SPU::ORHIr16:
> - case SPU::ORHIi8i16:
> - case SPU::ORBIv16i8:
> - case SPU::ORBIr8:
> - case SPU::ORIi16i32:
> - case SPU::ORIi8i32:
> - case SPU::AHIvec:
> - case SPU::AHIr16:
> - case SPU::AIv4i32:
> - assert(MI.getNumOperands() == 3 &&
> - MI.getOperand(0).isReg() &&
> - MI.getOperand(1).isReg() &&
> - MI.getOperand(2).isImm() &&
> - "invalid SPU ORI/ORHI/ORBI/AHI/AI/SFI/SFHI instruction!");
> - if (MI.getOperand(2).getImm() == 0) {
> - sourceReg = MI.getOperand(1).getReg();
> - destReg = MI.getOperand(0).getReg();
> - return true;
> - }
> - break;
> - case SPU::AIr32:
> - assert(MI.getNumOperands() == 3 &&
> - "wrong number of operands to AIr32");
> - if (MI.getOperand(0).isReg() &&
> - MI.getOperand(1).isReg() &&
> - (MI.getOperand(2).isImm() &&
> - MI.getOperand(2).getImm() == 0)) {
> - sourceReg = MI.getOperand(1).getReg();
> - destReg = MI.getOperand(0).getReg();
> - return true;
> - }
> - break;
> - case SPU::LRr8:
> - case SPU::LRr16:
> - case SPU::LRr32:
> - case SPU::LRf32:
> - case SPU::LRr64:
> - case SPU::LRf64:
> - case SPU::LRr128:
> - case SPU::LRv16i8:
> - case SPU::LRv8i16:
> - case SPU::LRv4i32:
> - case SPU::LRv4f32:
> - case SPU::LRv2i64:
> - case SPU::LRv2f64:
> - case SPU::ORv16i8_i8:
> - case SPU::ORv8i16_i16:
> - case SPU::ORv4i32_i32:
> - case SPU::ORv2i64_i64:
> - case SPU::ORv4f32_f32:
> - case SPU::ORv2f64_f64:
> - case SPU::ORi8_v16i8:
> - case SPU::ORi16_v8i16:
> - case SPU::ORi32_v4i32:
> - case SPU::ORi64_v2i64:
> - case SPU::ORf32_v4f32:
> - case SPU::ORf64_v2f64:
> -/*
> - case SPU::ORi128_r64:
> - case SPU::ORi128_f64:
> - case SPU::ORi128_r32:
> - case SPU::ORi128_f32:
> - case SPU::ORi128_r16:
> - case SPU::ORi128_r8:
> -*/
> - case SPU::ORi128_vec:
> -/*
> - case SPU::ORr64_i128:
> - case SPU::ORf64_i128:
> - case SPU::ORr32_i128:
> - case SPU::ORf32_i128:
> - case SPU::ORr16_i128:
> - case SPU::ORr8_i128:
> -*/
> - case SPU::ORvec_i128:
> -/*
> - case SPU::ORr16_r32:
> - case SPU::ORr8_r32:
> - case SPU::ORf32_r32:
> - case SPU::ORr32_f32:
> - case SPU::ORr32_r16:
> - case SPU::ORr32_r8:
> - case SPU::ORr16_r64:
> - case SPU::ORr8_r64:
> - case SPU::ORr64_r16:
> - case SPU::ORr64_r8:
> -*/
> - case SPU::ORr64_r32:
> - case SPU::ORr32_r64:
> - case SPU::ORf32_r32:
> - case SPU::ORr32_f32:
> - case SPU::ORf64_r64:
> - case SPU::ORr64_f64: {
> - assert(MI.getNumOperands() == 2 &&
> - MI.getOperand(0).isReg() &&
> - MI.getOperand(1).isReg() &&
> - "invalid SPU OR<type>_<vec> or LR instruction!");
> - sourceReg = MI.getOperand(1).getReg();
> - destReg = MI.getOperand(0).getReg();
> - return true;
> - break;
> - }
> - case SPU::ORv16i8:
> - case SPU::ORv8i16:
> - case SPU::ORv4i32:
> - case SPU::ORv2i64:
> - case SPU::ORr8:
> - case SPU::ORr16:
> - case SPU::ORr32:
> - case SPU::ORr64:
> - case SPU::ORr128:
> - case SPU::ORf32:
> - case SPU::ORf64:
> - assert(MI.getNumOperands() == 3 &&
> - MI.getOperand(0).isReg() &&
> - MI.getOperand(1).isReg() &&
> - MI.getOperand(2).isReg() &&
> - "invalid SPU OR(vec|r32|r64|gprc) instruction!");
> - if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
> - sourceReg = MI.getOperand(1).getReg();
> - destReg = MI.getOperand(0).getReg();
> - return true;
> - }
> - break;
> - }
> -
> - return false;
> -}
> -
> unsigned
> SPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
> int &FrameIndex) const {
>
> Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h
> URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff
>
==============================================================================
> --- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h (original)
> +++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h Fri Jul 16 17:35:46 2010
> @@ -32,12 +32,6 @@
> ///
> virtual const SPURegisterInfo &getRegisterInfo() const { return RI; }
>
> - /// Return true if the instruction is a register to register move and
return
> - /// the source and dest operands and their sub-register indices by
reference.
> - virtual bool isMoveInstr(const MachineInstr &MI,
> - unsigned &SrcReg, unsigned &DstReg,
> - unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
> -
> unsigned isLoadFromStackSlot(const MachineInstr *MI,
> int &FrameIndex) const;
> unsigned isStoreToStackSlot(const MachineInstr *MI,
>
> Modified: llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.cpp
> URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff
>
==============================================================================
> --- llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.cpp Fri Jul 16 17:35:46
2010
> @@ -30,41 +30,6 @@
> return op.isImm() && op.getImm() == 0;
> }
>
> -/// Return true if the instruction is a register to register move and
> -/// leave the source and dest operands in the passed parameters.
> -bool MBlazeInstrInfo::
> -isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg,
> - unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
> - SrcSubIdx = DstSubIdx = 0; // No sub-registers.
> -
> - // add $dst, $src, $zero || addu $dst, $zero, $src
> - // or $dst, $src, $zero || or $dst, $zero, $src
> - if ((MI.getOpcode() == MBlaze::ADD) || (MI.getOpcode() == MBlaze::OR)) {
> - if (MI.getOperand(1).isReg() && MI.getOperand(1).getReg() == MBlaze::R0)
{
> - DstReg = MI.getOperand(0).getReg();
> - SrcReg = MI.getOperand(2).getReg();
> - return true;
> - } else if (MI.getOperand(2).isReg() &&
> - MI.getOperand(2).getReg() == MBlaze::R0) {
> - DstReg = MI.getOperand(0).getReg();
> - SrcReg = MI.getOperand(1).getReg();
> - return true;
> - }
> - }
> -
> - // addi $dst, $src, 0
> - // ori $dst, $src, 0
> - if ((MI.getOpcode() == MBlaze::ADDI) || (MI.getOpcode() == MBlaze::ORI))
{
> - if ((MI.getOperand(1).isReg()) && (isZeroImm(MI.getOperand(2)))) {
> - DstReg = MI.getOperand(0).getReg();
> - SrcReg = MI.getOperand(1).getReg();
> - return true;
> - }
> - }
> -
> - return false;
> -}
> -
> /// isLoadFromStackSlot - If the specified machine instruction is a direct
> /// load from a stack slot, return the virtual or physical register number
of
> /// the destination along with the FrameIndex of the loaded stack slot. If
>
> Modified: llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.h
> URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff
>
==============================================================================
> --- llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.h (original)
> +++ llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.h Fri Jul 16 17:35:46
2010
> @@ -173,12 +173,6 @@
> ///
> virtual const MBlazeRegisterInfo &getRegisterInfo() const { return RI; }
>
> - /// Return true if the instruction is a register to register move and
return
> - /// the source and dest operands and their sub-register indices by
reference.
> - virtual bool isMoveInstr(const MachineInstr &MI,
> - unsigned &SrcReg, unsigned &DstReg,
> - unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
> -
> /// isLoadFromStackSlot - If the specified machine instruction is a direct
> /// load from a stack slot, return the virtual or physical register number
of
> /// the destination along with the FrameIndex of the loaded stack slot. If
>
> Modified: llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp
> URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff
>
==============================================================================
> --- llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp Fri Jul 16 17:35:46
2010
> @@ -100,27 +100,6 @@
> }
>
> bool
> -MSP430InstrInfo::isMoveInstr(const MachineInstr& MI,
> - unsigned &SrcReg, unsigned &DstReg,
> - unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
> - SrcSubIdx = DstSubIdx = 0; // No sub-registers yet.
> -
> - switch (MI.getOpcode()) {
> - default:
> - return false;
> - case MSP430::MOV8rr:
> - case MSP430::MOV16rr:
> - assert(MI.getNumOperands() >= 2 &&
> - MI.getOperand(0).isReg() &&
> - MI.getOperand(1).isReg() &&
> - "invalid register-register move instruction");
> - SrcReg = MI.getOperand(1).getReg();
> - DstReg = MI.getOperand(0).getReg();
> - return true;
> - }
> -}
> -
> -bool
> MSP430InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
> MachineBasicBlock::iterator MI,
> const std::vector<CalleeSavedInfo> &CSI,
>
> Modified: llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.h
> URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff
>
==============================================================================
> --- llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.h (original)
> +++ llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.h Fri Jul 16 17:35:46
2010
> @@ -54,10 +54,6 @@
> unsigned DestReg, unsigned SrcReg,
> bool KillSrc) const;
>
> - bool isMoveInstr(const MachineInstr& MI,
> - unsigned &SrcReg, unsigned &DstReg,
> - unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
> -
> virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
> MachineBasicBlock::iterator MI,
> unsigned SrcReg, bool isKill,
>
> Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp
> URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff
>
==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp Fri Jul 16 17:35:46 2010
> @@ -30,53 +30,6 @@
> return op.isImm() && op.getImm() == 0;
> }
>
> -/// Return true if the instruction is a register to register move and
> -/// leave the source and dest operands in the passed parameters.
> -bool MipsInstrInfo::
> -isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg,
> - unsigned &SrcSubIdx, unsigned &DstSubIdx) const
> -{
> - SrcSubIdx = DstSubIdx = 0; // No sub-registers.
> -
> - // addu $dst, $src, $zero || addu $dst, $zero, $src
> - // or $dst, $src, $zero || or $dst, $zero, $src
> - if ((MI.getOpcode() == Mips::ADDu) || (MI.getOpcode() == Mips::OR)) {
> - if (MI.getOperand(1).getReg() == Mips::ZERO) {
> - DstReg = MI.getOperand(0).getReg();
> - SrcReg = MI.getOperand(2).getReg();
> - return true;
> - } else if (MI.getOperand(2).getReg() == Mips::ZERO) {
> - DstReg = MI.getOperand(0).getReg();
> - SrcReg = MI.getOperand(1).getReg();
> - return true;
> - }
> - }
> -
> - // mov $fpDst, $fpSrc
> - // mfc $gpDst, $fpSrc
> - // mtc $fpDst, $gpSrc
> - if (MI.getOpcode() == Mips::FMOV_S32 ||
> - MI.getOpcode() == Mips::FMOV_D32 ||
> - MI.getOpcode() == Mips::MFC1 ||
> - MI.getOpcode() == Mips::MTC1 ||
> - MI.getOpcode() == Mips::MOVCCRToCCR) {
> - DstReg = MI.getOperand(0).getReg();
> - SrcReg = MI.getOperand(1).getReg();
> - return true;
> - }
> -
> - // addiu $dst, $src, 0
> - if (MI.getOpcode() == Mips::ADDiu) {
> - if ((MI.getOperand(1).isReg()) && (isZeroImm(MI.getOperand(2)))) {
> - DstReg = MI.getOperand(0).getReg();
> - SrcReg = MI.getOperand(1).getReg();
> - return true;
> - }
> - }
> -
> - return false;
> -}
> -
> /// isLoadFromStackSlot - If the specified machine instruction is a direct
> /// load from a stack slot, return the virtual or physical register number
of
> /// the destination along with the FrameIndex of the loaded stack slot. If
>
> Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.h
> URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff
>
==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.h (original)
> +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.h Fri Jul 16 17:35:46 2010
> @@ -174,12 +174,6 @@
> ///
> virtual const MipsRegisterInfo &getRegisterInfo() const { return RI; }
>
> - /// Return true if the instruction is a register to register move and
return
> - /// the source and dest operands and their sub-register indices by
reference.
> - virtual bool isMoveInstr(const MachineInstr &MI,
> - unsigned &SrcReg, unsigned &DstReg,
> - unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
> -
> /// isLoadFromStackSlot - If the specified machine instruction is a direct
> /// load from a stack slot, return the virtual or physical register number
of
> /// the destination along with the FrameIndex of the loaded stack slot. If
>
> Modified: llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.cpp
> URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff
>
==============================================================================
> --- llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.cpp Fri Jul 16 17:35:46
2010
> @@ -167,21 +167,6 @@
> .addReg(SrcReg, getKillRegState(KillSrc));
> }
>
> -bool PIC16InstrInfo::isMoveInstr(const MachineInstr &MI,
> - unsigned &SrcReg, unsigned &DestReg,
> - unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
> - SrcSubIdx = DstSubIdx = 0; // No sub-registers.
> -
> - if (MI.getOpcode() == PIC16::copy_fsr
> - || MI.getOpcode() == PIC16::copy_w) {
> - DestReg = MI.getOperand(0).getReg();
> - SrcReg = MI.getOperand(1).getReg();
> - return true;
> - }
> -
> - return false;
> -}
> -
> /// InsertBranch - Insert a branch into the end of the specified
> /// MachineBasicBlock. This operands to this method are the same as those
> /// returned by AnalyzeBranch. This is invoked in cases where
AnalyzeBranch
>
> Modified: llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.h
> URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff
>
==============================================================================
> --- llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.h (original)
> +++ llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.h Fri Jul 16 17:35:46 2010
> @@ -61,10 +61,6 @@
> MachineBasicBlock::iterator I, DebugLoc DL,
> unsigned DestReg, unsigned SrcReg,
> bool KillSrc) const;
> - virtual bool isMoveInstr(const MachineInstr &MI,
> - unsigned &SrcReg, unsigned &DstReg,
> - unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
> -
> virtual
> unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
> MachineBasicBlock *FBB,
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
> URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff
>
==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Fri Jul 16 17:35:46
2010
> @@ -39,67 +39,6 @@
> : TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm),
> RI(*TM.getSubtargetImpl(), *this) {}
>
> -bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
> - unsigned& sourceReg,
> - unsigned& destReg,
> - unsigned& sourceSubIdx,
> - unsigned& destSubIdx) const {
> - sourceSubIdx = destSubIdx = 0; // No sub-registers.
> -
> - unsigned oc = MI.getOpcode();
> - if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR ||
> - oc == PPC::OR4To8 || oc == PPC::OR8To4) { // or r1, r2, r2
> - assert(MI.getNumOperands() >= 3 &&
> - MI.getOperand(0).isReg() &&
> - MI.getOperand(1).isReg() &&
> - MI.getOperand(2).isReg() &&
> - "invalid PPC OR instruction!");
> - if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
> - sourceReg = MI.getOperand(1).getReg();
> - destReg = MI.getOperand(0).getReg();
> - return true;
> - }
> - } else if (oc == PPC::ADDI) { // addi r1, r2, 0
> - assert(MI.getNumOperands() >= 3 &&
> - MI.getOperand(0).isReg() &&
> - MI.getOperand(2).isImm() &&
> - "invalid PPC ADDI instruction!");
> - if (MI.getOperand(1).isReg() && MI.getOperand(2).getImm() == 0) {
> - sourceReg = MI.getOperand(1).getReg();
> - destReg = MI.getOperand(0).getReg();
> - return true;
> - }
> - } else if (oc == PPC::ORI) { // ori r1, r2, 0
> - assert(MI.getNumOperands() >= 3 &&
> - MI.getOperand(0).isReg() &&
> - MI.getOperand(1).isReg() &&
> - MI.getOperand(2).isImm() &&
> - "invalid PPC ORI instruction!");
> - if (MI.getOperand(2).getImm() == 0) {
> - sourceReg = MI.getOperand(1).getReg();
> - destReg = MI.getOperand(0).getReg();
> - return true;
> - }
> - } else if (oc == PPC::FMR) { // fmr r1, r2
> - assert(MI.getNumOperands() >= 2 &&
> - MI.getOperand(0).isReg() &&
> - MI.getOperand(1).isReg() &&
> - "invalid PPC FMR instruction");
> - sourceReg = MI.getOperand(1).getReg();
> - destReg = MI.getOperand(0).getReg();
> - return true;
> - } else if (oc == PPC::MCRF) { // mcrf cr1, cr2
> - assert(MI.getNumOperands() >= 2 &&
> - MI.getOperand(0).isReg() &&
> - MI.getOperand(1).isReg() &&
> - "invalid PPC MCRF instruction");
> - sourceReg = MI.getOperand(1).getReg();
> - destReg = MI.getOperand(0).getReg();
> - return true;
> - }
> - return false;
> -}
> -
> unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
> int &FrameIndex) const {
> switch (MI->getOpcode()) {
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h
> URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff
>
==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h Fri Jul 16 17:35:46 2010
> @@ -82,12 +82,6 @@
> ///
> virtual const PPCRegisterInfo &getRegisterInfo() const { return RI; }
>
> - /// Return true if the instruction is a register to register move and
return
> - /// the source and dest operands and their sub-register indices by
reference.
> - virtual bool isMoveInstr(const MachineInstr &MI,
> - unsigned &SrcReg, unsigned &DstReg,
> - unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
> -
> unsigned isLoadFromStackSlot(const MachineInstr *MI,
> int &FrameIndex) const;
> unsigned isStoreToStackSlot(const MachineInstr *MI,
>
> Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp
> URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff
>
==============================================================================
> --- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp Fri Jul 16 17:35:46
2010
> @@ -28,46 +28,6 @@
> RI(ST, *this), Subtarget(ST) {
> }
>
> -static bool isZeroImm(const MachineOperand &op) {
> - return op.isImm() && op.getImm() == 0;
> -}
> -
> -/// Return true if the instruction is a register to register move and
> -/// leave the source and dest operands in the passed parameters.
> -///
> -bool SparcInstrInfo::isMoveInstr(const MachineInstr &MI,
> - unsigned &SrcReg, unsigned &DstReg,
> - unsigned &SrcSR, unsigned &DstSR) const {
> - SrcSR = DstSR = 0; // No sub-registers.
> -
> - // We look for 3 kinds of patterns here:
> - // or with G0 or 0
> - // add with G0 or 0
> - // fmovs or FpMOVD (pseudo double move).
> - if (MI.getOpcode() == SP::ORrr || MI.getOpcode() == SP::ADDrr) {
> - if (MI.getOperand(1).getReg() == SP::G0) {
> - DstReg = MI.getOperand(0).getReg();
> - SrcReg = MI.getOperand(2).getReg();
> - return true;
> - } else if (MI.getOperand(2).getReg() == SP::G0) {
> - DstReg = MI.getOperand(0).getReg();
> - SrcReg = MI.getOperand(1).getReg();
> - return true;
> - }
> - } else if ((MI.getOpcode() == SP::ORri || MI.getOpcode() == SP::ADDri)
&&
> - isZeroImm(MI.getOperand(2)) && MI.getOperand(1).isReg()) {
> - DstReg = MI.getOperand(0).getReg();
> - SrcReg = MI.getOperand(1).getReg();
> - return true;
> - } else if (MI.getOpcode() == SP::FMOVS || MI.getOpcode() == SP::FpMOVD
||
> - MI.getOpcode() == SP::FMOVD) {
> - SrcReg = MI.getOperand(1).getReg();
> - DstReg = MI.getOperand(0).getReg();
> - return true;
> - }
> - return false;
> -}
> -
> /// isLoadFromStackSlot - If the specified machine instruction is a direct
> /// load from a stack slot, return the virtual or physical register number
of
> /// the destination along with the FrameIndex of the loaded stack slot. If
>
> Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h
> URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff
>
==============================================================================
> --- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h (original)
> +++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h Fri Jul 16 17:35:46 2010
> @@ -43,12 +43,6 @@
> ///
> virtual const SparcRegisterInfo &getRegisterInfo() const { return RI; }
>
> - /// Return true if the instruction is a register to register move and
return
> - /// the source and dest operands and their sub-register indices by
reference.
> - virtual bool isMoveInstr(const MachineInstr &MI,
> - unsigned &SrcReg, unsigned &DstReg,
> - unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
> -
> /// isLoadFromStackSlot - If the specified machine instruction is a direct
> /// load from a stack slot, return the virtual or physical register number
of
> /// the destination along with the FrameIndex of the loaded stack slot. If
>
> Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp
> URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff
>
==============================================================================
> --- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp Fri Jul 16 17:35:46
2010
> @@ -141,31 +141,6 @@
> .addReg(SrcReg, getKillRegState(KillSrc));
> }
>
> -bool
> -SystemZInstrInfo::isMoveInstr(const MachineInstr& MI,
> - unsigned &SrcReg, unsigned &DstReg,
> - unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
> - switch (MI.getOpcode()) {
> - default:
> - return false;
> - case SystemZ::MOV32rr:
> - case SystemZ::MOV64rr:
> - case SystemZ::MOV64rrP:
> - case SystemZ::MOV128rr:
> - case SystemZ::FMOV32rr:
> - case SystemZ::FMOV64rr:
> - assert(MI.getNumOperands() >= 2 &&
> - MI.getOperand(0).isReg() &&
> - MI.getOperand(1).isReg() &&
> - "invalid register-register move instruction");
> - SrcReg = MI.getOperand(1).getReg();
> - DstReg = MI.getOperand(0).getReg();
> - SrcSubIdx = MI.getOperand(1).getSubReg();
> - DstSubIdx = MI.getOperand(0).getSubReg();
> - return true;
> - }
> -}
> -
> unsigned SystemZInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
> int &FrameIndex) const {
> switch (MI->getOpcode()) {
>
> Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h
> URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff
>
==============================================================================
> --- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h (original)
> +++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h Fri Jul 16 17:35:46
2010
> @@ -65,9 +65,6 @@
> unsigned DestReg, unsigned SrcReg,
> bool KillSrc) const;
>
> - bool isMoveInstr(const MachineInstr& MI,
> - unsigned &SrcReg, unsigned &DstReg,
> - unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
> unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex)
const;
> unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex)
const;
>
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
> URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff
>
==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Fri Jul 16 17:35:46 2010
> @@ -667,46 +667,6 @@
> assert(AmbEntries.empty() && "Duplicated entries in unfolding maps?");
> }
>
> -bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
> - unsigned &SrcReg, unsigned &DstReg,
> - unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
> - switch (MI.getOpcode()) {
> - default:
> - return false;
> - case X86::MOV8rr:
> - case X86::MOV8rr_NOREX:
> - case X86::MOV16rr:
> - case X86::MOV32rr:
> - case X86::MOV64rr:
> - case X86::MOV32rr_TC:
> - case X86::MOV64rr_TC:
> -
> - // FP Stack register class copies
> - case X86::MOV_Fp3232: case X86::MOV_Fp6464: case X86::MOV_Fp8080:
> - case X86::MOV_Fp3264: case X86::MOV_Fp3280:
> - case X86::MOV_Fp6432: case X86::MOV_Fp8032:
> -
> - // Note that MOVSSrr and MOVSDrr are not considered copies. FR32 and
FR64
> - // copies are done with FsMOVAPSrr and FsMOVAPDrr.
> -
> - case X86::FsMOVAPSrr:
> - case X86::FsMOVAPDrr:
> - case X86::MOVAPSrr:
> - case X86::MOVAPDrr:
> - case X86::MOVDQArr:
> - case X86::MMX_MOVQ64rr:
> - assert(MI.getNumOperands() >= 2 &&
> - MI.getOperand(0).isReg() &&
> - MI.getOperand(1).isReg() &&
> - "invalid register-register move instruction");
> - SrcReg = MI.getOperand(1).getReg();
> - DstReg = MI.getOperand(0).getReg();
> - SrcSubIdx = MI.getOperand(1).getSubReg();
> - DstSubIdx = MI.getOperand(0).getSubReg();
> - return true;
> - }
> -}
> -
> bool
> X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
> unsigned &SrcReg, unsigned &DstReg,
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.h
> URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff
>
==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrInfo.h (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.h Fri Jul 16 17:35:46 2010
> @@ -610,12 +610,6 @@
> ///
> virtual const X86RegisterInfo &getRegisterInfo() const { return RI; }
>
> - /// Return true if the instruction is a register to register move and
return
> - /// the source and dest operands and their sub-register indices by
reference.
> - virtual bool isMoveInstr(const MachineInstr &MI,
> - unsigned &SrcReg, unsigned &DstReg,
> - unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
> -
> /// isCoalescableExtInstr - Return true if the instruction is a
"coalescable"
> /// extension instruction. That is, it's like a copy where it's legal for
the
> /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this
returns
>
> Modified: llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp
> URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff
>
==============================================================================
> --- llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp Fri Jul 16 17:35:46
2010
> @@ -46,33 +46,6 @@
> return op.isImm() && op.getImm() == 0;
> }
>
> -/// Return true if the instruction is a register to register move and
> -/// leave the source and dest operands in the passed parameters.
> -///
> -bool XCoreInstrInfo::isMoveInstr(const MachineInstr &MI,
> - unsigned &SrcReg, unsigned &DstReg,
> - unsigned &SrcSR, unsigned &DstSR) const {
> - SrcSR = DstSR = 0; // No sub-registers.
> -
> - // We look for 4 kinds of patterns here:
> - // add dst, src, 0
> - // sub dst, src, 0
> - // or dst, src, src
> - // and dst, src, src
> - if ((MI.getOpcode() == XCore::ADD_2rus || MI.getOpcode() ==
XCore::SUB_2rus)
> - && isZeroImm(MI.getOperand(2))) {
> - DstReg = MI.getOperand(0).getReg();
> - SrcReg = MI.getOperand(1).getReg();
> - return true;
> - } else if ((MI.getOpcode() == XCore::OR_3r || MI.getOpcode() ==
XCore::AND_3r)
> - && MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
> - DstReg = MI.getOperand(0).getReg();
> - SrcReg = MI.getOperand(1).getReg();
> - return true;
> - }
> - return false;
> -}
> -
> /// isLoadFromStackSlot - If the specified machine instruction is a direct
> /// load from a stack slot, return the virtual or physical register number
of
> /// the destination along with the FrameIndex of the loaded stack slot. If
>
> Modified: llvm/trunk/lib/Target/XCore/XCoreInstrInfo.h
> URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff
>
==============================================================================
> --- llvm/trunk/lib/Target/XCore/XCoreInstrInfo.h (original)
> +++ llvm/trunk/lib/Target/XCore/XCoreInstrInfo.h Fri Jul 16 17:35:46 2010
> @@ -30,12 +30,6 @@
> ///
> virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; }
>
> - /// Return true if the instruction is a register to register move and
return
> - /// the source and dest operands and their sub-register indices by
reference.
> - virtual bool isMoveInstr(const MachineInstr &MI,
> - unsigned &SrcReg, unsigned &DstReg,
> - unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
> -
> /// isLoadFromStackSlot - If the specified machine instruction is a direct
> /// load from a stack slot, return the virtual or physical register number
of
> /// the destination along with the FrameIndex of the loaded stack slot. If
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20100717/8500cf0d/attachment.html>
More information about the llvm-commits
mailing list