<p>Thanks!</p>
<p>On Jul 16, 2010 6:38 PM, "Jakob Stoklund Olesen" <<a href="mailto:stoklund@2pi.dk">stoklund@2pi.dk</a>> wrote:<br type="attribution">> Author: stoklund<br>> Date: Fri Jul 16 17:35:46 2010<br>> New Revision: 108567<br>
> <br>> URL: <a href="http://llvm.org/viewvc/llvm-project?rev=108567&view=rev">http://llvm.org/viewvc/llvm-project?rev=108567&view=rev</a><br>> Log:<br>> Remove the isMoveInstr() hook.<br>> <br>> Modified:<br>
> llvm/trunk/docs/WritingAnLLVMBackend.html<br>> llvm/trunk/include/llvm/Target/TargetInstrInfo.h<br>> llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp<br>> llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h<br>
> llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp<br>> llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h<br>> llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.cpp<br>> llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.h<br>
> llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp<br>> llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h<br>> llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.cpp<br>> llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.h<br>
> llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp<br>> llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.h<br>> llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp<br>> llvm/trunk/lib/Target/Mips/MipsInstrInfo.h<br>
> llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.cpp<br>> llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.h<br>> llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp<br>> llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h<br>
> llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp<br>> llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h<br>> llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp<br>> llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h<br>
> llvm/trunk/lib/Target/X86/X86InstrInfo.cpp<br>> llvm/trunk/lib/Target/X86/X86InstrInfo.h<br>> llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp<br>> llvm/trunk/lib/Target/XCore/XCoreInstrInfo.h<br>
> <br>> Modified: llvm/trunk/docs/WritingAnLLVMBackend.html<br>> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/WritingAnLLVMBackend.html?rev=108567&r1=108566&r2=108567&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/WritingAnLLVMBackend.html?rev=108567&r1=108566&r2=108567&view=diff</a><br>
> ==============================================================================<br>> --- llvm/trunk/docs/WritingAnLLVMBackend.html (original)<br>> +++ llvm/trunk/docs/WritingAnLLVMBackend.html Fri Jul 16 17:35:46 2010<br>
> @@ -1299,9 +1299,6 @@<br>> </p><br>> <br>> <ul><br>> -<li><tt>isMoveInstr</tt> — Return true if the instruction is a register to<br>> - register move; false, otherwise.</li><br>
> -<br>> <li><tt>isLoadFromStackSlot</tt> — If the specified machine instruction is<br>> a direct load from a stack slot, return the register number of the<br>> destination and the <tt>FrameIndex</tt> of the stack slot.</li><br>
> <br>> Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h<br>> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff</a><br>
> ==============================================================================<br>> --- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original)<br>> +++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Fri Jul 16 17:35:46 2010<br>
> @@ -92,15 +92,6 @@<br>> AliasAnalysis *AA) const;<br>> <br>> public:<br>> - /// isMoveInstr - Return true if the instruction is a register to register<br>
> - /// move and return the source and dest operands and their sub-register<br>> - /// indices by reference.<br>> - virtual bool isMoveInstr(const MachineInstr& MI,<br>> - unsigned& SrcReg, unsigned& DstReg,<br>
> - unsigned& SrcSubIdx, unsigned& DstSubIdx) const {<br>> - return false;<br>> - }<br>> -<br>> /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"<br>
> /// extension instruction. That is, it's like a copy where it's legal for the<br>> /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns<br>> <br>> Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff</a><br>
> ==============================================================================<br>> --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)<br>> +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Fri Jul 16 17:35:46 2010<br>
> @@ -573,48 +573,6 @@<br>> return 0; // Not reached<br>> }<br>> <br>> -/// Return true if the instruction is a register to register move and<br>> -/// leave the source and dest operands in the passed parameters.<br>
> -///<br>> -bool<br>> -ARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI,<br>> - unsigned &SrcReg, unsigned &DstReg,<br>> - unsigned& SrcSubIdx, unsigned& DstSubIdx) const {<br>
> - switch (MI.getOpcode()) {<br>> - default: break;<br>> - case ARM::VMOVS:<br>> - case ARM::VMOVD:<br>> - case ARM::VMOVDneon:<br>> - case ARM::VMOVQ:<br>> - case ARM::VMOVQQ : {<br>> - SrcReg = MI.getOperand(1).getReg();<br>
> - DstReg = MI.getOperand(0).getReg();<br>> - SrcSubIdx = MI.getOperand(1).getSubReg();<br>> - DstSubIdx = MI.getOperand(0).getSubReg();<br>> - return true;<br>> - }<br>> - case ARM::MOVr:<br>
> - case ARM::MOVr_TC:<br>> - case ARM::tMOVr:<br>> - case ARM::tMOVgpr2tgpr:<br>> - case ARM::tMOVtgpr2gpr:<br>> - case ARM::tMOVgpr2gpr:<br>> - case ARM::t2MOVr: {<br>> - assert(MI.getDesc().getNumOperands() >= 2 &&<br>
> - MI.getOperand(0).isReg() &&<br>> - MI.getOperand(1).isReg() &&<br>> - "Invalid ARM MOV instruction");<br>> - SrcReg = MI.getOperand(1).getReg();<br>
> - DstReg = MI.getOperand(0).getReg();<br>> - SrcSubIdx = MI.getOperand(1).getSubReg();<br>> - DstSubIdx = MI.getOperand(0).getSubReg();<br>> - return true;<br>> - }<br>> - }<br>> -<br>
> - return false;<br>> -}<br>> -<br>> unsigned<br>> ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,<br>> int &FrameIndex) const {<br>> <br>> Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff</a><br>
> ==============================================================================<br>> --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h (original)<br>> +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h Fri Jul 16 17:35:46 2010<br>
> @@ -262,12 +262,6 @@<br>> ///<br>> virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;<br>> <br>> - /// Return true if the instruction is a register to register move and return<br>> - /// the source and dest operands and their sub-register indices by reference.<br>
> - virtual bool isMoveInstr(const MachineInstr &MI,<br>> - unsigned &SrcReg, unsigned &DstReg,<br>> - unsigned &SrcSubIdx, unsigned &DstSubIdx) const;<br>
> -<br>> virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,<br>> int &FrameIndex) const;<br>> virtual unsigned isStoreToStackSlot(const MachineInstr *MI,<br>
> <br>> Modified: llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp<br>> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff</a><br>
> ==============================================================================<br>> --- llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp (original)<br>> +++ llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp Fri Jul 16 17:35:46 2010<br>
> @@ -27,32 +27,6 @@<br>> RI(*this) { }<br>> <br>> <br>> -bool AlphaInstrInfo::isMoveInstr(const MachineInstr& MI,<br>> - unsigned& sourceReg, unsigned& destReg,<br>
> - unsigned& SrcSR, unsigned& DstSR) const {<br>> - unsigned oc = MI.getOpcode();<br>> - if (oc == Alpha::BISr || <br>> - oc == Alpha::CPYSS || <br>> - oc == Alpha::CPYST ||<br>
> - oc == Alpha::CPYSSt || <br>> - oc == Alpha::CPYSTs) {<br>> - // or r1, r2, r2 <br>> - // cpys(s|t) r1 r2 r2<br>> - assert(MI.getNumOperands() >= 3 &&<br>> - MI.getOperand(0).isReg() &&<br>
> - MI.getOperand(1).isReg() &&<br>> - MI.getOperand(2).isReg() &&<br>> - "invalid Alpha BIS instruction!");<br>> - if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {<br>
> - sourceReg = MI.getOperand(1).getReg();<br>> - destReg = MI.getOperand(0).getReg();<br>> - SrcSR = DstSR = 0;<br>> - return true;<br>> - }<br>> - }<br>> - return false;<br>
> -}<br>> -<br>> unsigned <br>> AlphaInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,<br>> int &FrameIndex) const {<br>> <br>> Modified: llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff</a><br>
> ==============================================================================<br>> --- llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h (original)<br>> +++ llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h Fri Jul 16 17:35:46 2010<br>
> @@ -30,12 +30,6 @@<br>> ///<br>> virtual const AlphaRegisterInfo &getRegisterInfo() const { return RI; }<br>> <br>> - /// Return true if the instruction is a register to register move and return<br>
> - /// the source and dest operands and their sub-register indices by reference.<br>> - virtual bool isMoveInstr(const MachineInstr &MI,<br>> - unsigned &SrcReg, unsigned &DstReg,<br>
> - unsigned &SrcSubIdx, unsigned &DstSubIdx) const;<br>> - <br>> virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,<br>> int &FrameIndex) const;<br>
> virtual unsigned isStoreToStackSlot(const MachineInstr *MI,<br>> <br>> Modified: llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.cpp<br>> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff</a><br>
> ==============================================================================<br>> --- llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.cpp (original)<br>> +++ llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.cpp Fri Jul 16 17:35:46 2010<br>
> @@ -28,34 +28,6 @@<br>> RI(ST, *this),<br>> Subtarget(ST) {}<br>> <br>> -/// Return true if the instruction is a register to register move and<br>> -/// leave the source and dest operands in the passed parameters.<br>
> -bool BlackfinInstrInfo::isMoveInstr(const MachineInstr &MI,<br>> - unsigned &SrcReg,<br>> - unsigned &DstReg,<br>> - unsigned &SrcSR,<br>
> - unsigned &DstSR) const {<br>> - SrcSR = DstSR = 0; // No sub-registers.<br>> - switch (MI.getOpcode()) {<br>> - case BF::MOVE:<br>> - case BF::MOVE_ncccc:<br>> - case BF::MOVE_ccncc:<br>
> - case BF::MOVECC_zext:<br>> - case BF::MOVECC_nz:<br>> - DstReg = MI.getOperand(0).getReg();<br>> - SrcReg = MI.getOperand(1).getReg();<br>> - return true;<br>> - case BF::SLL16i:<br>> - if (MI.getOperand(2).getImm()!=0)<br>
> - return false;<br>> - DstReg = MI.getOperand(0).getReg();<br>> - SrcReg = MI.getOperand(1).getReg();<br>> - return true;<br>> - default:<br>> - return false;<br>> - }<br>> -}<br>
> -<br>> /// isLoadFromStackSlot - If the specified machine instruction is a direct<br>> /// load from a stack slot, return the virtual or physical register number of<br>> /// the destination along with the FrameIndex of the loaded stack slot. If<br>
> <br>> Modified: llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.h<br>> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff</a><br>
> ==============================================================================<br>> --- llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.h (original)<br>> +++ llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.h Fri Jul 16 17:35:46 2010<br>
> @@ -30,10 +30,6 @@<br>> /// always be able to get register info as well (through this method).<br>> virtual const BlackfinRegisterInfo &getRegisterInfo() const { return RI; }<br>> <br>> - virtual bool isMoveInstr(const MachineInstr &MI,<br>
> - unsigned &SrcReg, unsigned &DstReg,<br>> - unsigned &SrcSubIdx, unsigned &DstSubIdx) const;<br>> -<br>> virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,<br>
> int &FrameIndex) const;<br>> <br>> <br>> Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp<br>> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff</a><br>
> ==============================================================================<br>> --- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp (original)<br>> +++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp Fri Jul 16 17:35:46 2010<br>
> @@ -54,148 +54,6 @@<br>> RI(*TM.getSubtargetImpl(), *this)<br>> { /* NOP */ }<br>> <br>> -bool<br>> -SPUInstrInfo::isMoveInstr(const MachineInstr& MI,<br>> - unsigned& sourceReg,<br>
> - unsigned& destReg,<br>> - unsigned& SrcSR, unsigned& DstSR) const {<br>> - SrcSR = DstSR = 0; // No sub-registers.<br>> -<br>> - switch (MI.getOpcode()) {<br>
> - default:<br>> - break;<br>> - case SPU::ORIv4i32:<br>> - case SPU::ORIr32:<br>> - case SPU::ORHIv8i16:<br>> - case SPU::ORHIr16:<br>> - case SPU::ORHIi8i16:<br>> - case SPU::ORBIv16i8:<br>
> - case SPU::ORBIr8:<br>> - case SPU::ORIi16i32:<br>> - case SPU::ORIi8i32:<br>> - case SPU::AHIvec:<br>> - case SPU::AHIr16:<br>> - case SPU::AIv4i32:<br>> - assert(MI.getNumOperands() == 3 &&<br>
> - MI.getOperand(0).isReg() &&<br>> - MI.getOperand(1).isReg() &&<br>> - MI.getOperand(2).isImm() &&<br>> - "invalid SPU ORI/ORHI/ORBI/AHI/AI/SFI/SFHI instruction!");<br>
> - if (MI.getOperand(2).getImm() == 0) {<br>> - sourceReg = MI.getOperand(1).getReg();<br>> - destReg = MI.getOperand(0).getReg();<br>> - return true;<br>> - }<br>> - break;<br>> - case SPU::AIr32:<br>
> - assert(MI.getNumOperands() == 3 &&<br>> - "wrong number of operands to AIr32");<br>> - if (MI.getOperand(0).isReg() &&<br>> - MI.getOperand(1).isReg() &&<br>
> - (MI.getOperand(2).isImm() &&<br>> - MI.getOperand(2).getImm() == 0)) {<br>> - sourceReg = MI.getOperand(1).getReg();<br>> - destReg = MI.getOperand(0).getReg();<br>> - return true;<br>
> - }<br>> - break;<br>> - case SPU::LRr8:<br>> - case SPU::LRr16:<br>> - case SPU::LRr32:<br>> - case SPU::LRf32:<br>> - case SPU::LRr64:<br>> - case SPU::LRf64:<br>> - case SPU::LRr128:<br>
> - case SPU::LRv16i8:<br>> - case SPU::LRv8i16:<br>> - case SPU::LRv4i32:<br>> - case SPU::LRv4f32:<br>> - case SPU::LRv2i64:<br>> - case SPU::LRv2f64:<br>> - case SPU::ORv16i8_i8:<br>> - case SPU::ORv8i16_i16:<br>
> - case SPU::ORv4i32_i32:<br>> - case SPU::ORv2i64_i64:<br>> - case SPU::ORv4f32_f32:<br>> - case SPU::ORv2f64_f64:<br>> - case SPU::ORi8_v16i8:<br>> - case SPU::ORi16_v8i16:<br>> - case SPU::ORi32_v4i32:<br>
> - case SPU::ORi64_v2i64:<br>> - case SPU::ORf32_v4f32:<br>> - case SPU::ORf64_v2f64:<br>> -/*<br>> - case SPU::ORi128_r64:<br>> - case SPU::ORi128_f64:<br>> - case SPU::ORi128_r32:<br>> - case SPU::ORi128_f32:<br>
> - case SPU::ORi128_r16:<br>> - case SPU::ORi128_r8:<br>> -*/<br>> - case SPU::ORi128_vec:<br>> -/*<br>> - case SPU::ORr64_i128:<br>> - case SPU::ORf64_i128:<br>> - case SPU::ORr32_i128:<br>
> - case SPU::ORf32_i128:<br>> - case SPU::ORr16_i128:<br>> - case SPU::ORr8_i128:<br>> -*/<br>> - case SPU::ORvec_i128:<br>> -/*<br>> - case SPU::ORr16_r32:<br>> - case SPU::ORr8_r32:<br>> - case SPU::ORf32_r32:<br>
> - case SPU::ORr32_f32:<br>> - case SPU::ORr32_r16:<br>> - case SPU::ORr32_r8:<br>> - case SPU::ORr16_r64:<br>> - case SPU::ORr8_r64:<br>> - case SPU::ORr64_r16:<br>> - case SPU::ORr64_r8:<br>
> -*/<br>> - case SPU::ORr64_r32:<br>> - case SPU::ORr32_r64:<br>> - case SPU::ORf32_r32:<br>> - case SPU::ORr32_f32:<br>> - case SPU::ORf64_r64:<br>> - case SPU::ORr64_f64: {<br>> - assert(MI.getNumOperands() == 2 &&<br>
> - MI.getOperand(0).isReg() &&<br>> - MI.getOperand(1).isReg() &&<br>> - "invalid SPU OR<type>_<vec> or LR instruction!");<br>> - sourceReg = MI.getOperand(1).getReg();<br>
> - destReg = MI.getOperand(0).getReg();<br>> - return true;<br>> - break;<br>> - }<br>> - case SPU::ORv16i8:<br>> - case SPU::ORv8i16:<br>> - case SPU::ORv4i32:<br>> - case SPU::ORv2i64:<br>
> - case SPU::ORr8:<br>> - case SPU::ORr16:<br>> - case SPU::ORr32:<br>> - case SPU::ORr64:<br>> - case SPU::ORr128:<br>> - case SPU::ORf32:<br>> - case SPU::ORf64:<br>> - assert(MI.getNumOperands() == 3 &&<br>
> - MI.getOperand(0).isReg() &&<br>> - MI.getOperand(1).isReg() &&<br>> - MI.getOperand(2).isReg() &&<br>> - "invalid SPU OR(vec|r32|r64|gprc) instruction!");<br>
> - if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {<br>> - sourceReg = MI.getOperand(1).getReg();<br>> - destReg = MI.getOperand(0).getReg();<br>> - return true;<br>> - }<br>
> - break;<br>> - }<br>> -<br>> - return false;<br>> -}<br>> -<br>> unsigned<br>> SPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,<br>> int &FrameIndex) const {<br>
> <br>> Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h<br>> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff</a><br>
> ==============================================================================<br>> --- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h (original)<br>> +++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h Fri Jul 16 17:35:46 2010<br>
> @@ -32,12 +32,6 @@<br>> ///<br>> virtual const SPURegisterInfo &getRegisterInfo() const { return RI; }<br>> <br>> - /// Return true if the instruction is a register to register move and return<br>
> - /// the source and dest operands and their sub-register indices by reference.<br>> - virtual bool isMoveInstr(const MachineInstr &MI,<br>> - unsigned &SrcReg, unsigned &DstReg,<br>
> - unsigned &SrcSubIdx, unsigned &DstSubIdx) const;<br>> -<br>> unsigned isLoadFromStackSlot(const MachineInstr *MI,<br>> int &FrameIndex) const;<br>
> unsigned isStoreToStackSlot(const MachineInstr *MI,<br>> <br>> Modified: llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.cpp<br>> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff</a><br>
> ==============================================================================<br>> --- llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.cpp (original)<br>> +++ llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.cpp Fri Jul 16 17:35:46 2010<br>
> @@ -30,41 +30,6 @@<br>> return op.isImm() && op.getImm() == 0;<br>> }<br>> <br>> -/// Return true if the instruction is a register to register move and<br>> -/// leave the source and dest operands in the passed parameters.<br>
> -bool MBlazeInstrInfo::<br>> -isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg,<br>> - unsigned &SrcSubIdx, unsigned &DstSubIdx) const {<br>> - SrcSubIdx = DstSubIdx = 0; // No sub-registers.<br>
> -<br>> - // add $dst, $src, $zero || addu $dst, $zero, $src<br>> - // or $dst, $src, $zero || or $dst, $zero, $src<br>> - if ((MI.getOpcode() == MBlaze::ADD) || (MI.getOpcode() == MBlaze::OR)) {<br>> - if (MI.getOperand(1).isReg() && MI.getOperand(1).getReg() == MBlaze::R0) {<br>
> - DstReg = MI.getOperand(0).getReg();<br>> - SrcReg = MI.getOperand(2).getReg();<br>> - return true;<br>> - } else if (MI.getOperand(2).isReg() && <br>> - MI.getOperand(2).getReg() == MBlaze::R0) {<br>
> - DstReg = MI.getOperand(0).getReg();<br>> - SrcReg = MI.getOperand(1).getReg();<br>> - return true;<br>> - }<br>> - }<br>> -<br>> - // addi $dst, $src, 0<br>> - // ori $dst, $src, 0<br>
> - if ((MI.getOpcode() == MBlaze::ADDI) || (MI.getOpcode() == MBlaze::ORI)) {<br>> - if ((MI.getOperand(1).isReg()) && (isZeroImm(MI.getOperand(2)))) {<br>> - DstReg = MI.getOperand(0).getReg();<br>
> - SrcReg = MI.getOperand(1).getReg();<br>> - return true;<br>> - }<br>> - }<br>> -<br>> - return false;<br>> -}<br>> -<br>> /// isLoadFromStackSlot - If the specified machine instruction is a direct<br>
> /// load from a stack slot, return the virtual or physical register number of<br>> /// the destination along with the FrameIndex of the loaded stack slot. If<br>> <br>> Modified: llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.h<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff</a><br>
> ==============================================================================<br>> --- llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.h (original)<br>> +++ llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.h Fri Jul 16 17:35:46 2010<br>
> @@ -173,12 +173,6 @@<br>> ///<br>> virtual const MBlazeRegisterInfo &getRegisterInfo() const { return RI; }<br>> <br>> - /// Return true if the instruction is a register to register move and return<br>
> - /// the source and dest operands and their sub-register indices by reference.<br>> - virtual bool isMoveInstr(const MachineInstr &MI,<br>> - unsigned &SrcReg, unsigned &DstReg,<br>
> - unsigned &SrcSubIdx, unsigned &DstSubIdx) const;<br>> -<br>> /// isLoadFromStackSlot - If the specified machine instruction is a direct<br>> /// load from a stack slot, return the virtual or physical register number of<br>
> /// the destination along with the FrameIndex of the loaded stack slot. If<br>> <br>> Modified: llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp<br>> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff</a><br>
> ==============================================================================<br>> --- llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp (original)<br>> +++ llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp Fri Jul 16 17:35:46 2010<br>
> @@ -100,27 +100,6 @@<br>> }<br>> <br>> bool<br>> -MSP430InstrInfo::isMoveInstr(const MachineInstr& MI,<br>> - unsigned &SrcReg, unsigned &DstReg,<br>> - unsigned &SrcSubIdx, unsigned &DstSubIdx) const {<br>
> - SrcSubIdx = DstSubIdx = 0; // No sub-registers yet.<br>> -<br>> - switch (MI.getOpcode()) {<br>> - default:<br>> - return false;<br>> - case MSP430::MOV8rr:<br>> - case MSP430::MOV16rr:<br>
> - assert(MI.getNumOperands() >= 2 &&<br>> - MI.getOperand(0).isReg() &&<br>> - MI.getOperand(1).isReg() &&<br>> - "invalid register-register move instruction");<br>
> - SrcReg = MI.getOperand(1).getReg();<br>> - DstReg = MI.getOperand(0).getReg();<br>> - return true;<br>> - }<br>> -}<br>> -<br>> -bool<br>> MSP430InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,<br>
> MachineBasicBlock::iterator MI,<br>> const std::vector<CalleeSavedInfo> &CSI,<br>> <br>> Modified: llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.h<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff</a><br>
> ==============================================================================<br>> --- llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.h (original)<br>> +++ llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.h Fri Jul 16 17:35:46 2010<br>
> @@ -54,10 +54,6 @@<br>> unsigned DestReg, unsigned SrcReg,<br>> bool KillSrc) const;<br>> <br>> - bool isMoveInstr(const MachineInstr& MI,<br>> - unsigned &SrcReg, unsigned &DstReg,<br>
> - unsigned &SrcSubIdx, unsigned &DstSubIdx) const;<br>> -<br>> virtual void storeRegToStackSlot(MachineBasicBlock &MBB,<br>> MachineBasicBlock::iterator MI,<br>
> unsigned SrcReg, bool isKill,<br>> <br>> Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp<br>> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff</a><br>
> ==============================================================================<br>> --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp (original)<br>> +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp Fri Jul 16 17:35:46 2010<br>
> @@ -30,53 +30,6 @@<br>> return op.isImm() && op.getImm() == 0;<br>> }<br>> <br>> -/// Return true if the instruction is a register to register move and<br>> -/// leave the source and dest operands in the passed parameters.<br>
> -bool MipsInstrInfo::<br>> -isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg,<br>> - unsigned &SrcSubIdx, unsigned &DstSubIdx) const <br>> -{<br>> - SrcSubIdx = DstSubIdx = 0; // No sub-registers.<br>
> -<br>> - // addu $dst, $src, $zero || addu $dst, $zero, $src<br>> - // or $dst, $src, $zero || or $dst, $zero, $src<br>> - if ((MI.getOpcode() == Mips::ADDu) || (MI.getOpcode() == Mips::OR)) {<br>> - if (MI.getOperand(1).getReg() == Mips::ZERO) {<br>
> - DstReg = MI.getOperand(0).getReg();<br>> - SrcReg = MI.getOperand(2).getReg();<br>> - return true;<br>> - } else if (MI.getOperand(2).getReg() == Mips::ZERO) {<br>> - DstReg = MI.getOperand(0).getReg();<br>
> - SrcReg = MI.getOperand(1).getReg();<br>> - return true;<br>> - }<br>> - }<br>> -<br>> - // mov $fpDst, $fpSrc<br>> - // mfc $gpDst, $fpSrc<br>> - // mtc $fpDst, $gpSrc<br>> - if (MI.getOpcode() == Mips::FMOV_S32 || <br>
> - MI.getOpcode() == Mips::FMOV_D32 || <br>> - MI.getOpcode() == Mips::MFC1 || <br>> - MI.getOpcode() == Mips::MTC1 ||<br>> - MI.getOpcode() == Mips::MOVCCRToCCR) {<br>> - DstReg = MI.getOperand(0).getReg();<br>
> - SrcReg = MI.getOperand(1).getReg();<br>> - return true;<br>> - }<br>> -<br>> - // addiu $dst, $src, 0<br>> - if (MI.getOpcode() == Mips::ADDiu) {<br>> - if ((MI.getOperand(1).isReg()) && (isZeroImm(MI.getOperand(2)))) {<br>
> - DstReg = MI.getOperand(0).getReg();<br>> - SrcReg = MI.getOperand(1).getReg();<br>> - return true;<br>> - }<br>> - }<br>> -<br>> - return false;<br>> -}<br>> -<br>> /// isLoadFromStackSlot - If the specified machine instruction is a direct<br>
> /// load from a stack slot, return the virtual or physical register number of<br>> /// the destination along with the FrameIndex of the loaded stack slot. If<br>> <br>> Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.h<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff</a><br>
> ==============================================================================<br>> --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.h (original)<br>> +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.h Fri Jul 16 17:35:46 2010<br>
> @@ -174,12 +174,6 @@<br>> ///<br>> virtual const MipsRegisterInfo &getRegisterInfo() const { return RI; }<br>> <br>> - /// Return true if the instruction is a register to register move and return<br>
> - /// the source and dest operands and their sub-register indices by reference.<br>> - virtual bool isMoveInstr(const MachineInstr &MI,<br>> - unsigned &SrcReg, unsigned &DstReg,<br>
> - unsigned &SrcSubIdx, unsigned &DstSubIdx) const;<br>> - <br>> /// isLoadFromStackSlot - If the specified machine instruction is a direct<br>> /// load from a stack slot, return the virtual or physical register number of<br>
> /// the destination along with the FrameIndex of the loaded stack slot. If<br>> <br>> Modified: llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.cpp<br>> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff</a><br>
> ==============================================================================<br>> --- llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.cpp (original)<br>> +++ llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.cpp Fri Jul 16 17:35:46 2010<br>
> @@ -167,21 +167,6 @@<br>> .addReg(SrcReg, getKillRegState(KillSrc));<br>> }<br>> <br>> -bool PIC16InstrInfo::isMoveInstr(const MachineInstr &MI,<br>> - unsigned &SrcReg, unsigned &DestReg,<br>
> - unsigned &SrcSubIdx, unsigned &DstSubIdx) const {<br>> - SrcSubIdx = DstSubIdx = 0; // No sub-registers.<br>> -<br>> - if (MI.getOpcode() == PIC16::copy_fsr<br>> - || MI.getOpcode() == PIC16::copy_w) {<br>
> - DestReg = MI.getOperand(0).getReg();<br>> - SrcReg = MI.getOperand(1).getReg();<br>> - return true;<br>> - }<br>> -<br>> - return false;<br>> -}<br>> -<br>> /// InsertBranch - Insert a branch into the end of the specified<br>
> /// MachineBasicBlock. This operands to this method are the same as those<br>> /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch<br>> <br>> Modified: llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.h<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff</a><br>
> ==============================================================================<br>> --- llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.h (original)<br>> +++ llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.h Fri Jul 16 17:35:46 2010<br>
> @@ -61,10 +61,6 @@<br>> MachineBasicBlock::iterator I, DebugLoc DL,<br>> unsigned DestReg, unsigned SrcReg,<br>> bool KillSrc) const;<br>
> - virtual bool isMoveInstr(const MachineInstr &MI,<br>> - unsigned &SrcReg, unsigned &DstReg,<br>> - unsigned &SrcSubIdx, unsigned &DstSubIdx) const;<br>
> -<br>> virtual <br>> unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,<br>> MachineBasicBlock *FBB,<br>> <br>> Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff</a><br>
> ==============================================================================<br>> --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (original)<br>> +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Fri Jul 16 17:35:46 2010<br>
> @@ -39,67 +39,6 @@<br>> : TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm),<br>> RI(*TM.getSubtargetImpl(), *this) {}<br>> <br>> -bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,<br>
> - unsigned& sourceReg,<br>> - unsigned& destReg,<br>> - unsigned& sourceSubIdx,<br>> - unsigned& destSubIdx) const {<br>
> - sourceSubIdx = destSubIdx = 0; // No sub-registers.<br>> -<br>> - unsigned oc = MI.getOpcode();<br>> - if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR ||<br>> - oc == PPC::OR4To8 || oc == PPC::OR8To4) { // or r1, r2, r2<br>
> - assert(MI.getNumOperands() >= 3 &&<br>> - MI.getOperand(0).isReg() &&<br>> - MI.getOperand(1).isReg() &&<br>> - MI.getOperand(2).isReg() &&<br>
> - "invalid PPC OR instruction!");<br>> - if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {<br>> - sourceReg = MI.getOperand(1).getReg();<br>> - destReg = MI.getOperand(0).getReg();<br>
> - return true;<br>> - }<br>> - } else if (oc == PPC::ADDI) { // addi r1, r2, 0<br>> - assert(MI.getNumOperands() >= 3 &&<br>> - MI.getOperand(0).isReg() &&<br>
> - MI.getOperand(2).isImm() &&<br>> - "invalid PPC ADDI instruction!");<br>> - if (MI.getOperand(1).isReg() && MI.getOperand(2).getImm() == 0) {<br>> - sourceReg = MI.getOperand(1).getReg();<br>
> - destReg = MI.getOperand(0).getReg();<br>> - return true;<br>> - }<br>> - } else if (oc == PPC::ORI) { // ori r1, r2, 0<br>> - assert(MI.getNumOperands() >= 3 &&<br>
> - MI.getOperand(0).isReg() &&<br>> - MI.getOperand(1).isReg() &&<br>> - MI.getOperand(2).isImm() &&<br>> - "invalid PPC ORI instruction!");<br>
> - if (MI.getOperand(2).getImm() == 0) {<br>> - sourceReg = MI.getOperand(1).getReg();<br>> - destReg = MI.getOperand(0).getReg();<br>> - return true;<br>> - }<br>> - } else if (oc == PPC::FMR) { // fmr r1, r2<br>
> - assert(MI.getNumOperands() >= 2 &&<br>> - MI.getOperand(0).isReg() &&<br>> - MI.getOperand(1).isReg() &&<br>> - "invalid PPC FMR instruction");<br>
> - sourceReg = MI.getOperand(1).getReg();<br>> - destReg = MI.getOperand(0).getReg();<br>> - return true;<br>> - } else if (oc == PPC::MCRF) { // mcrf cr1, cr2<br>> - assert(MI.getNumOperands() >= 2 &&<br>
> - MI.getOperand(0).isReg() &&<br>> - MI.getOperand(1).isReg() &&<br>> - "invalid PPC MCRF instruction");<br>> - sourceReg = MI.getOperand(1).getReg();<br>
> - destReg = MI.getOperand(0).getReg();<br>> - return true;<br>> - }<br>> - return false;<br>> -}<br>> -<br>> unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, <br>> int &FrameIndex) const {<br>
> switch (MI->getOpcode()) {<br>> <br>> Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h<br>> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff</a><br>
> ==============================================================================<br>> --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h (original)<br>> +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h Fri Jul 16 17:35:46 2010<br>
> @@ -82,12 +82,6 @@<br>> ///<br>> virtual const PPCRegisterInfo &getRegisterInfo() const { return RI; }<br>> <br>> - /// Return true if the instruction is a register to register move and return<br>
> - /// the source and dest operands and their sub-register indices by reference.<br>> - virtual bool isMoveInstr(const MachineInstr &MI,<br>> - unsigned &SrcReg, unsigned &DstReg,<br>
> - unsigned &SrcSubIdx, unsigned &DstSubIdx) const;<br>> -<br>> unsigned isLoadFromStackSlot(const MachineInstr *MI,<br>> int &FrameIndex) const;<br>
> unsigned isStoreToStackSlot(const MachineInstr *MI,<br>> <br>> Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp<br>> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff</a><br>
> ==============================================================================<br>> --- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp (original)<br>> +++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp Fri Jul 16 17:35:46 2010<br>
> @@ -28,46 +28,6 @@<br>> RI(ST, *this), Subtarget(ST) {<br>> }<br>> <br>> -static bool isZeroImm(const MachineOperand &op) {<br>> - return op.isImm() && op.getImm() == 0;<br>> -}<br>
> -<br>> -/// Return true if the instruction is a register to register move and<br>> -/// leave the source and dest operands in the passed parameters.<br>> -///<br>> -bool SparcInstrInfo::isMoveInstr(const MachineInstr &MI,<br>
> - unsigned &SrcReg, unsigned &DstReg,<br>> - unsigned &SrcSR, unsigned &DstSR) const {<br>> - SrcSR = DstSR = 0; // No sub-registers.<br>
> -<br>> - // We look for 3 kinds of patterns here:<br>> - // or with G0 or 0<br>> - // add with G0 or 0<br>> - // fmovs or FpMOVD (pseudo double move).<br>> - if (MI.getOpcode() == SP::ORrr || MI.getOpcode() == SP::ADDrr) {<br>
> - if (MI.getOperand(1).getReg() == SP::G0) {<br>> - DstReg = MI.getOperand(0).getReg();<br>> - SrcReg = MI.getOperand(2).getReg();<br>> - return true;<br>> - } else if (MI.getOperand(2).getReg() == SP::G0) {<br>
> - DstReg = MI.getOperand(0).getReg();<br>> - SrcReg = MI.getOperand(1).getReg();<br>> - return true;<br>> - }<br>> - } else if ((MI.getOpcode() == SP::ORri || MI.getOpcode() == SP::ADDri) &&<br>
> - isZeroImm(MI.getOperand(2)) && MI.getOperand(1).isReg()) {<br>> - DstReg = MI.getOperand(0).getReg();<br>> - SrcReg = MI.getOperand(1).getReg();<br>> - return true;<br>> - } else if (MI.getOpcode() == SP::FMOVS || MI.getOpcode() == SP::FpMOVD ||<br>
> - MI.getOpcode() == SP::FMOVD) {<br>> - SrcReg = MI.getOperand(1).getReg();<br>> - DstReg = MI.getOperand(0).getReg();<br>> - return true;<br>> - }<br>> - return false;<br>> -}<br>
> -<br>> /// isLoadFromStackSlot - If the specified machine instruction is a direct<br>> /// load from a stack slot, return the virtual or physical register number of<br>> /// the destination along with the FrameIndex of the loaded stack slot. If<br>
> <br>> Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h<br>> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff</a><br>
> ==============================================================================<br>> --- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h (original)<br>> +++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h Fri Jul 16 17:35:46 2010<br>
> @@ -43,12 +43,6 @@<br>> ///<br>> virtual const SparcRegisterInfo &getRegisterInfo() const { return RI; }<br>> <br>> - /// Return true if the instruction is a register to register move and return<br>
> - /// the source and dest operands and their sub-register indices by reference.<br>> - virtual bool isMoveInstr(const MachineInstr &MI,<br>> - unsigned &SrcReg, unsigned &DstReg,<br>
> - unsigned &SrcSubIdx, unsigned &DstSubIdx) const;<br>> - <br>> /// isLoadFromStackSlot - If the specified machine instruction is a direct<br>> /// load from a stack slot, return the virtual or physical register number of<br>
> /// the destination along with the FrameIndex of the loaded stack slot. If<br>> <br>> Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp<br>> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff</a><br>
> ==============================================================================<br>> --- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp (original)<br>> +++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp Fri Jul 16 17:35:46 2010<br>
> @@ -141,31 +141,6 @@<br>> .addReg(SrcReg, getKillRegState(KillSrc));<br>> }<br>> <br>> -bool<br>> -SystemZInstrInfo::isMoveInstr(const MachineInstr& MI,<br>> - unsigned &SrcReg, unsigned &DstReg,<br>
> - unsigned &SrcSubIdx, unsigned &DstSubIdx) const {<br>> - switch (MI.getOpcode()) {<br>> - default:<br>> - return false;<br>> - case SystemZ::MOV32rr:<br>> - case SystemZ::MOV64rr:<br>
> - case SystemZ::MOV64rrP:<br>> - case SystemZ::MOV128rr:<br>> - case SystemZ::FMOV32rr:<br>> - case SystemZ::FMOV64rr:<br>> - assert(MI.getNumOperands() >= 2 &&<br>> - MI.getOperand(0).isReg() &&<br>
> - MI.getOperand(1).isReg() &&<br>> - "invalid register-register move instruction");<br>> - SrcReg = MI.getOperand(1).getReg();<br>> - DstReg = MI.getOperand(0).getReg();<br>
> - SrcSubIdx = MI.getOperand(1).getSubReg();<br>> - DstSubIdx = MI.getOperand(0).getSubReg();<br>> - return true;<br>> - }<br>> -}<br>> -<br>> unsigned SystemZInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,<br>
> int &FrameIndex) const {<br>> switch (MI->getOpcode()) {<br>> <br>> Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h<br>> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff</a><br>
> ==============================================================================<br>> --- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h (original)<br>> +++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h Fri Jul 16 17:35:46 2010<br>
> @@ -65,9 +65,6 @@<br>> unsigned DestReg, unsigned SrcReg,<br>> bool KillSrc) const;<br>> <br>> - bool isMoveInstr(const MachineInstr& MI,<br>> - unsigned &SrcReg, unsigned &DstReg,<br>
> - unsigned &SrcSubIdx, unsigned &DstSubIdx) const;<br>> unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;<br>> unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const;<br>
> <br>> <br>> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp<br>> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff</a><br>
> ==============================================================================<br>> --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)<br>> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Fri Jul 16 17:35:46 2010<br>
> @@ -667,46 +667,6 @@<br>> assert(AmbEntries.empty() && "Duplicated entries in unfolding maps?");<br>> }<br>> <br>> -bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,<br>> - unsigned &SrcReg, unsigned &DstReg,<br>
> - unsigned &SrcSubIdx, unsigned &DstSubIdx) const {<br>> - switch (MI.getOpcode()) {<br>> - default:<br>> - return false;<br>> - case X86::MOV8rr:<br>> - case X86::MOV8rr_NOREX:<br>
> - case X86::MOV16rr:<br>> - case X86::MOV32rr: <br>> - case X86::MOV64rr:<br>> - case X86::MOV32rr_TC: <br>> - case X86::MOV64rr_TC:<br>> -<br>> - // FP Stack register class copies<br>> - case X86::MOV_Fp3232: case X86::MOV_Fp6464: case X86::MOV_Fp8080:<br>
> - case X86::MOV_Fp3264: case X86::MOV_Fp3280:<br>> - case X86::MOV_Fp6432: case X86::MOV_Fp8032:<br>> -<br>> - // Note that MOVSSrr and MOVSDrr are not considered copies. FR32 and FR64<br>> - // copies are done with FsMOVAPSrr and FsMOVAPDrr.<br>
> -<br>> - case X86::FsMOVAPSrr:<br>> - case X86::FsMOVAPDrr:<br>> - case X86::MOVAPSrr:<br>> - case X86::MOVAPDrr:<br>> - case X86::MOVDQArr:<br>> - case X86::MMX_MOVQ64rr:<br>> - assert(MI.getNumOperands() >= 2 &&<br>
> - MI.getOperand(0).isReg() &&<br>> - MI.getOperand(1).isReg() &&<br>> - "invalid register-register move instruction");<br>> - SrcReg = MI.getOperand(1).getReg();<br>
> - DstReg = MI.getOperand(0).getReg();<br>> - SrcSubIdx = MI.getOperand(1).getSubReg();<br>> - DstSubIdx = MI.getOperand(0).getSubReg();<br>> - return true;<br>> - }<br>> -}<br>> -<br>> bool<br>
> X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,<br>> unsigned &SrcReg, unsigned &DstReg,<br>> <br>> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.h<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff</a><br>
> ==============================================================================<br>> --- llvm/trunk/lib/Target/X86/X86InstrInfo.h (original)<br>> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.h Fri Jul 16 17:35:46 2010<br>
> @@ -610,12 +610,6 @@<br>> ///<br>> virtual const X86RegisterInfo &getRegisterInfo() const { return RI; }<br>> <br>> - /// Return true if the instruction is a register to register move and return<br>
> - /// the source and dest operands and their sub-register indices by reference.<br>> - virtual bool isMoveInstr(const MachineInstr &MI,<br>> - unsigned &SrcReg, unsigned &DstReg,<br>
> - unsigned &SrcSubIdx, unsigned &DstSubIdx) const;<br>> -<br>> /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"<br>> /// extension instruction. That is, it's like a copy where it's legal for the<br>
> /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns<br>> <br>> Modified: llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp<br>> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff</a><br>
> ==============================================================================<br>> --- llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp (original)<br>> +++ llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp Fri Jul 16 17:35:46 2010<br>
> @@ -46,33 +46,6 @@<br>> return op.isImm() && op.getImm() == 0;<br>> }<br>> <br>> -/// Return true if the instruction is a register to register move and<br>> -/// leave the source and dest operands in the passed parameters.<br>
> -///<br>> -bool XCoreInstrInfo::isMoveInstr(const MachineInstr &MI,<br>> - unsigned &SrcReg, unsigned &DstReg,<br>> - unsigned &SrcSR, unsigned &DstSR) const {<br>
> - SrcSR = DstSR = 0; // No sub-registers.<br>> -<br>> - // We look for 4 kinds of patterns here:<br>> - // add dst, src, 0<br>> - // sub dst, src, 0<br>> - // or dst, src, src<br>> - // and dst, src, src<br>
> - if ((MI.getOpcode() == XCore::ADD_2rus || MI.getOpcode() == XCore::SUB_2rus)<br>> - && isZeroImm(MI.getOperand(2))) {<br>> - DstReg = MI.getOperand(0).getReg();<br>> - SrcReg = MI.getOperand(1).getReg();<br>
> - return true;<br>> - } else if ((MI.getOpcode() == XCore::OR_3r || MI.getOpcode() == XCore::AND_3r)<br>> - && MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {<br>> - DstReg = MI.getOperand(0).getReg();<br>
> - SrcReg = MI.getOperand(1).getReg();<br>> - return true;<br>> - }<br>> - return false;<br>> -}<br>> -<br>> /// isLoadFromStackSlot - If the specified machine instruction is a direct<br>> /// load from a stack slot, return the virtual or physical register number of<br>
> /// the destination along with the FrameIndex of the loaded stack slot. If<br>> <br>> Modified: llvm/trunk/lib/Target/XCore/XCoreInstrInfo.h<br>> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff</a><br>
> ==============================================================================<br>> --- llvm/trunk/lib/Target/XCore/XCoreInstrInfo.h (original)<br>> +++ llvm/trunk/lib/Target/XCore/XCoreInstrInfo.h Fri Jul 16 17:35:46 2010<br>
> @@ -30,12 +30,6 @@<br>> ///<br>> virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; }<br>> <br>> - /// Return true if the instruction is a register to register move and return<br>
> - /// the source and dest operands and their sub-register indices by reference.<br>> - virtual bool isMoveInstr(const MachineInstr &MI,<br>> - unsigned &SrcReg, unsigned &DstReg,<br>
> - unsigned &SrcSubIdx, unsigned &DstSubIdx) const;<br>> - <br>> /// isLoadFromStackSlot - If the specified machine instruction is a direct<br>> /// load from a stack slot, return the virtual or physical register number of<br>
> /// the destination along with the FrameIndex of the loaded stack slot. If<br>> <br>> <br>> _______________________________________________<br>> llvm-commits mailing list<br>> <a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br>
> <a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits">http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</a><br></p>