[llvm-commits] [llvm] r103828 - /llvm/trunk/lib/CodeGen/RegAllocFast.cpp
Jakob Stoklund Olesen
stoklund at 2pi.dk
Fri May 14 15:02:56 PDT 2010
Author: stoklund
Date: Fri May 14 17:02:56 2010
New Revision: 103828
URL: http://llvm.org/viewvc/llvm-project?rev=103828&view=rev
Log:
Track allocatable instead of reserved regs, and never take an unallocatable hint.
Modified:
llvm/trunk/lib/CodeGen/RegAllocFast.cpp
Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocFast.cpp?rev=103828&r1=103827&r2=103828&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocFast.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocFast.cpp Fri May 14 17:02:56 2010
@@ -108,8 +108,8 @@
// instruction, and so cannot be allocated.
BitVector UsedInInstr;
- // ReservedRegs - vector of reserved physical registers.
- BitVector ReservedRegs;
+ // Allocatable - vector of allocatable physical registers.
+ BitVector Allocatable;
// atEndOfBlock - This flag is set after allocating all instructions in a
// block, before emitting final spills. When it is set, LiveRegMap is no
@@ -394,7 +394,8 @@
// Ignore invalid hints.
if (Hint && (!TargetRegisterInfo::isPhysicalRegister(Hint) ||
- !RC->contains(Hint) || UsedInInstr.test(Hint)))
+ !RC->contains(Hint) || UsedInInstr.test(Hint)) ||
+ !Allocatable.test(Hint))
Hint = 0;
// If there is no hint, peek at the first use of this register.
@@ -404,7 +405,8 @@
// Copy to physreg -> use physreg as hint.
if (TII->isMoveInstr(MI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
SrcReg == VirtReg && TargetRegisterInfo::isPhysicalRegister(DstReg) &&
- RC->contains(DstReg) && !UsedInInstr.test(DstReg)) {
+ RC->contains(DstReg) && !UsedInInstr.test(DstReg) &&
+ Allocatable.test(DstReg)) {
Hint = DstReg;
DEBUG(dbgs() << "%reg" << VirtReg << " gets hint from " << MI);
}
@@ -413,7 +415,7 @@
// Take hint when possible.
if (Hint) {
assert(RC->contains(Hint) && !UsedInInstr.test(Hint) &&
- "Invalid hint should have been cleared");
+ Allocatable.test(Hint) && "Invalid hint should have been cleared");
switch(PhysRegState[Hint]) {
case regDisabled:
case regReserved:
@@ -674,7 +676,7 @@
VirtOpEnd = i+1;
continue;
}
- if (ReservedRegs.test(Reg)) continue;
+ if (!Allocatable.test(Reg)) continue;
if (MO.isUse()) {
usePhysReg(MO);
} else if (MO.isEarlyClobber()) {
@@ -729,7 +731,7 @@
unsigned Reg = MO.getReg();
if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
- if (ReservedRegs.test(Reg)) continue;
+ if (!Allocatable.test(Reg)) continue;
definePhysReg(MBB, MI, Reg, (MO.isImplicit() || MO.isDead()) ?
regFree : regReserved);
continue;
@@ -797,7 +799,7 @@
TII = TM->getInstrInfo();
UsedInInstr.resize(TRI->getNumRegs());
- ReservedRegs = TRI->getReservedRegs(*MF);
+ Allocatable = TRI->getAllocatableSet(*MF);
// initialize the virtual->physical register map to have a 'null'
// mapping for all virtual registers
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