[llvm-commits] [llvm] r98637 - in /llvm/trunk: ./ lib/Target/ARM/ lib/Target/ARM/AsmPrinter/ lib/Target/ARM/Disassembler/ test/CodeGen/ARM/ test/CodeGen/Thumb2/ utils/TableGen/

[Johnny Chen]

Sorry.  I meant zeroing the top two bytes of the 16-bit thumb instructions before
feeding it to the decoder which expects a 4-byte instruction in this case.

On Mar 16, 2010, at 9:51 AM, Johnny Chen wrote:

> Fixed length.  I treated Thumb/Thumb2 instructions as "fixed" length in this regard,
> zeroing the the top two bytes.  It is easier for me to generate the decoder function
> for Thumb/Thumb2 this way.
> 
> Thanks.
> 
> On Mar 16, 2010, at 9:45 AM, Anton Korobeynikov wrote:
> 
>> Hi, Johny
>> 
>>> Initial ARM/Thumb disassembler check-in.  It consists of a tablgen backend
>>> (RISCDisassemblerEmitter) which emits the decoder functions for ARM and Thumb,
>>> and the disassembler core which invokes the decoder function and builds up the
>>> MCInst based on the decoded Opcode.
>> Quick q: here RISC means "completely fixed length"? Or, say, the
>> instructions might be 16/32/24 bits length (contain 1/2 optional
>> address fields)?
>> 
>> -- 
>> With best regards, Anton Korobeynikov
>> Faculty of Mathematics and Mechanics, Saint Petersburg State University
>