[llvm-commits] [llvm] r91944 - in /llvm/trunk/lib/Target/ARM: ARMInstrThumb.td ARMRegisterInfo.td

[Chris Lattner]

On Dec 22, 2009, at 4:46 PM, Jakob Stoklund Olesen wrote:

>> 2. How to match this: If you really want dag isel to match these as  
>> loads, you'd need to write a pat pattern (or manual matching) that  
>> matches load(addr) and uses an SDNodeTransform to extract the  
>> immediate, maybe something like this:
>>
>> Pat<(load (t_addrmode_sp:$addr)),
>>   (tLDRspi (EXTRACT_IMM_FROM_ADDRMODE_SP t_addrmode_sp:$addr))>;
>>
>> Some simple examples of sdnode transforms are things like this from  
>> PPC:
>>
>> def : Pat<(i32 imm:$imm),
>>         (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
>>
>> Which matches an arbitrary 32-bit immediate with a "ori" and "lis"  
>> instruction to get the two 16-bit halves.
>
> IMHO, this is stretching the pattern matching too far. It is much  
> easier to write custom code to insert this kind of instruction. I  
> will try to figure out why ARM is pattern-matching an SP-relative  
> load.

Using custom code also works for me, thanks!

>
>>> I was trying to break as little as possible.
>>
>> I appreciate that, but single-register register classes aren't  
>> really register classes :).
>
> Of course. BTW, there is no need for you to look at the end of  
> BlackfinRegisterInfo.td. Ever. :-)

hehe, it's a deal! :)

-Chris