[llvm-commits] [llvm] r91944 - in /llvm/trunk/lib/Target/ARM: ARMInstrThumb.td ARMRegisterInfo.td

[Jakob Stoklund Olesen]

On Dec 22, 2009, at 4:29 PM, Chris Lattner wrote:

> 
> On Dec 22, 2009, at 4:17 PM, Jakob Stoklund Olesen wrote:
> 
>> 
>> On Dec 22, 2009, at 4:01 PM, Chris Lattner wrote:
>> 
>>> 
>>> On Dec 22, 2009, at 3:54 PM, Jakob Stoklund Olesen wrote:
>>> 
>>>> Author: stoklund
>>>> Date: Tue Dec 22 17:54:44 2009
>>>> New Revision: 91944
>>>> 
>>>> URL: http://llvm.org/viewvc/llvm-project?rev=91944&view=rev
>>>> Log:
>>>> Add a SPR register class to the ARM target.
>>>> 
>>>> Certain Thumb instructions require only SP (e.g. tSTRspi).
>>> 
>>> Hi Jakob,
>>> 
>>> If it only allows one register, doesn't it make more sense to make it an implicit reg operand instead of a regclass operand?
>> 
>> Maybe. How would it look in this pattern?
>> 
>> def t_addrmode_sp : Operand<i32>,
>>                   ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
>> let PrintMethod = "printThumbAddrModeSPOperand";
>> let MIOperandInfo = (ops JustSP:$base, i32imm:$offsimm);
>> }
> 
> Eww, gross.  :)  Two separate issues:

Yup :-)

> 1. How to model this:  This instruction should be modeled as taking SP as an implicit input, and take an i32imm operand.  I think this should be pretty simple and any non-isel code that generates this can easily adjust to not passing in SP.

Agreed. This would be the best way of representing that instruction.

> 2. How to match this: If you really want dag isel to match these as loads, you'd need to write a pat pattern (or manual matching) that matches load(addr) and uses an SDNodeTransform to extract the immediate, maybe something like this:
> 
> Pat<(load (t_addrmode_sp:$addr)),
>    (tLDRspi (EXTRACT_IMM_FROM_ADDRMODE_SP t_addrmode_sp:$addr))>;
> 
> Some simple examples of sdnode transforms are things like this from PPC:
> 
> def : Pat<(i32 imm:$imm),
>          (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
> 
> Which matches an arbitrary 32-bit immediate with a "ori" and "lis" instruction to get the two 16-bit halves.

IMHO, this is stretching the pattern matching too far. It is much easier to write custom code to insert this kind of instruction. I will try to figure out why ARM is pattern-matching an SP-relative load.

>> I was trying to break as little as possible.
> 
> I appreciate that, but single-register register classes aren't really register classes :).

Of course. BTW, there is no need for you to look at the end of BlackfinRegisterInfo.td. Ever. :-)

Thanks, Chris!

/jakob