[llvm-commits] [llvm] r78025 - in /llvm/trunk/lib/Target/ARM: ARMISelLowering.cpp ARMISelLowering.h ARMInstrNEON.td

[Bob Wilson]

On Aug 3, 2009, at 6:21 PM, Evan Cheng wrote:

> On Aug 3, 2009, at 5:36 PM, Bob Wilson wrote:
>
>>
>> +static SDValue LowerNeonVLDIntrinsic(SDValue Op, SelectionDAG &DAG,
>> +                                     unsigned Opcode, unsigned
>> NumVecs) {
>> +  SDNode *Node = Op.getNode();
>> +  MVT VT = Node->getValueType(0);
>> +  DebugLoc dl = Op.getDebugLoc();
>> +
>> +  if (!VT.is64BitVector())
>> +    return SDValue(); // unimplemented
>> +
>> +  SDValue Ops[] = { Node->getOperand(0),
>> +                    Node->getOperand(1) };
>> +  SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
>> +  SDValue Result = DAG.getNode(Opcode, dl, Tys, Ops, 2);
>> +
>> +  static const unsigned VLDRegs[] = {
>> +    ARM::D0, ARM::D1, ARM::D2, ARM::D3
>> +  };
>
> Is this a temporary solution? Perhaps we want to do a post-isel pre-
> allocation pass to be a little bit smarter about what registers to  
> pre-
> allocate to?

I was just doing it that way because you told me to do that (e.g., http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20090706/080830.html 
).  When we talked about it in person, it was my understanding that  
your plan was to do something very simple when legalizing the  
intrinsics and then later on we would investigate smarter solutions.

However, having gotten this far with it , I am not very happy with  
allocating the registers during isel lowering.  The CopyToReg and  
CopyFromReg nodes are a hassle, and taking the next step of generating  
machine instructions seems like it will be even more awkward.

I'm going to try adding a post-isel pre-allocation pass, as you suggest.

Take 3.