[llvm-commits] [llvm] r78025 - in /llvm/trunk/lib/Target/ARM: ARMISelLowering.cpp ARMISelLowering.h ARMInstrNEON.td

[Evan Cheng]

On Aug 3, 2009, at 5:36 PM, Bob Wilson wrote:

>
>
> +static SDValue LowerNeonVLDIntrinsic(SDValue Op, SelectionDAG &DAG,
> +                                     unsigned Opcode, unsigned  
> NumVecs) {
> +  SDNode *Node = Op.getNode();
> +  MVT VT = Node->getValueType(0);
> +  DebugLoc dl = Op.getDebugLoc();
> +
> +  if (!VT.is64BitVector())
> +    return SDValue(); // unimplemented
> +
> +  SDValue Ops[] = { Node->getOperand(0),
> +                    Node->getOperand(1) };
> +  SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
> +  SDValue Result = DAG.getNode(Opcode, dl, Tys, Ops, 2);
> +
> +  static const unsigned VLDRegs[] = {
> +    ARM::D0, ARM::D1, ARM::D2, ARM::D3
> +  };

Is this a temporary solution? Perhaps we want to do a post-isel pre- 
allocation pass to be a little bit smarter about what registers to pre- 
allocate to?

Evan

> +
> +  SmallVector<SDValue, 4> ResultVals;
> +  SDValue Chain = Result.getValue(0);
> +  SDValue Flag = Result.getValue(1);
> +  for (unsigned N = 0; N < NumVecs; ++N) {
> +    Chain = DAG.getCopyFromReg(Chain, dl, VLDRegs[N], VT,  
> Flag).getValue(1);
> +    ResultVals.push_back(Chain.getValue(0));
> +    Flag = Chain.getValue(2);
> +  }
> +  ResultVals.push_back(Chain);
> +  return DAG.getNode(ISD::MERGE_VALUES, dl, Node->getVTList(),
> +                     ResultVals.data(), NumVecs + 1);
> +}
> +
> +SDValue
> +ARMTargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG  
> &DAG) {
> +  unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))- 
> >getZExtValue();
> +  switch (IntNo) {
> +  case Intrinsic::arm_neon_vld2i:
> +  case Intrinsic::arm_neon_vld2f:
> +    return LowerNeonVLDIntrinsic(Op, DAG, ARMISD::VLD2D, 2);
> +  case Intrinsic::arm_neon_vld3i:
> +  case Intrinsic::arm_neon_vld3f:
> +    return LowerNeonVLDIntrinsic(Op, DAG, ARMISD::VLD3D, 3);
> +  case Intrinsic::arm_neon_vld4i:
> +  case Intrinsic::arm_neon_vld4f:
> +    return LowerNeonVLDIntrinsic(Op, DAG, ARMISD::VLD4D, 4);
> +  case Intrinsic::arm_neon_vst2i:
> +  case Intrinsic::arm_neon_vst2f:
> +  case Intrinsic::arm_neon_vst3i:
> +  case Intrinsic::arm_neon_vst3f:
> +  case Intrinsic::arm_neon_vst4i:
> +  case Intrinsic::arm_neon_vst4f:
> +  default: return SDValue();    // Don't custom lower most  
> intrinsics.
> +  }
> +}
> +
> SDValue
> ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG  
> &DAG) {
>   unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))- 
> >getZExtValue();
> @@ -2354,6 +2412,7 @@
>   case ISD::RETURNADDR:    break;
>   case ISD::FRAMEADDR:     return LowerFRAMEADDR(Op, DAG);
>   case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op,  
> DAG);
> +  case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op,  
> DAG);
>   case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op,  
> DAG);
>   case ISD::BIT_CONVERT:   return ExpandBIT_CONVERT(Op.getNode(),  
> DAG);
>   case ISD::SHL:
>
> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=78025&r1=78024&r2=78025&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original)
> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Mon Aug  3 19:36:16  
> 2009
> @@ -114,7 +114,12 @@
>       VGETLANEs,    // sign-extend vector extract element
>
>       // Vector duplicate lane (128-bit result only; 64-bit is a  
> shuffle)
> -      VDUPLANEQ     // splat a lane from a 64-bit vector to a 128- 
> bit vector
> +      VDUPLANEQ,    // splat a lane from a 64-bit vector to a 128- 
> bit vector
> +
> +      // Vector load/store with (de)interleaving
> +      VLD2D,
> +      VLD3D,
> +      VLD4D
>     };
>   }
>
> @@ -237,6 +242,7 @@
>     SDNode *LowerCallResult(SDValue Chain, SDValue InFlag,  
> CallSDNode *TheCall,
>                             unsigned CallingConv, SelectionDAG &DAG);
>     SDValue LowerCALL(SDValue Op, SelectionDAG &DAG);
> +    SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG);
>     SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG);
>     SDValue LowerRET(SDValue Op, SelectionDAG &DAG);
>     SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG);
>
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=78025&r1=78024&r2=78025&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Aug  3 19:36:16 2009
> @@ -68,6 +68,14 @@
> def NEONvduplaneq : SDNode<"ARMISD::VDUPLANEQ",
>                            SDTypeProfile<1, 2, [SDTCisVT<2, i32>]>>;
>
> +def SDTARMVLD     : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
> +def NEONvld2d     : SDNode<"ARMISD::VLD2D", SDTARMVLD,
> +                           [SDNPHasChain, SDNPOutFlag, SDNPMayLoad]>;
> +def NEONvld3d     : SDNode<"ARMISD::VLD3D", SDTARMVLD,
> +                           [SDNPHasChain, SDNPOutFlag, SDNPMayLoad]>;
> +def NEONvld4d     : SDNode<"ARMISD::VLD4D", SDTARMVLD,
> +                           [SDNPHasChain, SDNPOutFlag, SDNPMayLoad]>;
> +
> // 
> = 
> = 
> = 
> ----------------------------------------------------------------------= 
> ==//
> // NEON operand definitions
> // 
> = 
> = 
> = 
> ----------------------------------------------------------------------= 
> ==//
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits