[llvm-commits] [llvm] r77174 - in /llvm/trunk/lib/Target/ARM: ARMBaseInstrInfo.cpp Thumb1InstrInfo.cpp Thumb1InstrInfo.h
Evan Cheng
evan.cheng at apple.com
Sun Jul 26 17:24:37 PDT 2009
Author: evancheng
Date: Sun Jul 26 19:24:36 2009
New Revision: 77174
URL: http://llvm.org/viewvc/llvm-project?rev=77174&view=rev
Log:
Merge isLoadFromStackSlot into one since it behaves the same regardless of sub-target.
Modified:
llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp
llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.h
Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=77174&r1=77173&r2=77174&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Sun Jul 26 19:24:36 2009
@@ -491,6 +491,7 @@
SrcSubIdx = DstSubIdx = 0; // No sub-registers.
switch (MI.getOpcode()) {
+ default: break;
case ARM::FCPYS:
case ARM::FCPYD:
case ARM::VMOVD:
@@ -521,8 +522,10 @@
unsigned
ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
int &FrameIndex) const {
- unsigned oc = MI->getOpcode();
- if (oc == getOpcode(ARMII::LDRrr)) {
+ switch (MI->getOpcode()) {
+ default: break;
+ case ARM::LDR:
+ case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
if (MI->getOperand(1).isFI() &&
MI->getOperand(2).isReg() &&
MI->getOperand(3).isImm() &&
@@ -531,22 +534,25 @@
FrameIndex = MI->getOperand(1).getIndex();
return MI->getOperand(0).getReg();
}
- }
- else if (oc == getOpcode(ARMII::LDRri)) {
+ break;
+ case ARM::t2LDRi12:
+ case ARM::tRestore:
if (MI->getOperand(1).isFI() &&
MI->getOperand(2).isImm() &&
MI->getOperand(2).getImm() == 0) {
FrameIndex = MI->getOperand(1).getIndex();
return MI->getOperand(0).getReg();
}
- }
- else if (oc == ARM::FLDD || oc == ARM::FLDS) {
+ break;
+ case ARM::FLDD:
+ case ARM::FLDS:
if (MI->getOperand(1).isFI() &&
MI->getOperand(2).isImm() &&
MI->getOperand(2).getImm() == 0) {
FrameIndex = MI->getOperand(1).getIndex();
return MI->getOperand(0).getReg();
}
+ break;
}
return 0;
@@ -555,8 +561,10 @@
unsigned
ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
int &FrameIndex) const {
- unsigned oc = MI->getOpcode();
- if (oc == getOpcode(ARMII::STRrr)) {
+ switch (MI->getOpcode()) {
+ default: break;
+ case ARM::STR:
+ case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
if (MI->getOperand(1).isFI() &&
MI->getOperand(2).isReg() &&
MI->getOperand(3).isImm() &&
@@ -565,22 +573,25 @@
FrameIndex = MI->getOperand(1).getIndex();
return MI->getOperand(0).getReg();
}
- }
- else if (oc == getOpcode(ARMII::STRri)) {
+ break;
+ case ARM::t2STRi12:
+ case ARM::tSpill:
if (MI->getOperand(1).isFI() &&
MI->getOperand(2).isImm() &&
MI->getOperand(2).getImm() == 0) {
FrameIndex = MI->getOperand(1).getIndex();
return MI->getOperand(0).getReg();
}
- }
- else if (oc == ARM::FSTD || oc == ARM::FSTS) {
+ break;
+ case ARM::FSTD:
+ case ARM::FSTS:
if (MI->getOperand(1).isFI() &&
MI->getOperand(2).isImm() &&
MI->getOperand(2).getImm() == 0) {
FrameIndex = MI->getOperand(1).getIndex();
return MI->getOperand(0).getReg();
}
+ break;
}
return 0;
Modified: llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp?rev=77174&r1=77173&r2=77174&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp Sun Jul 26 19:24:36 2009
@@ -71,38 +71,6 @@
return false;
}
-unsigned Thumb1InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
- int &FrameIndex) const {
- switch (MI->getOpcode()) {
- default: break;
- case ARM::tRestore:
- if (MI->getOperand(1).isFI() &&
- MI->getOperand(2).isImm() &&
- MI->getOperand(2).getImm() == 0) {
- FrameIndex = MI->getOperand(1).getIndex();
- return MI->getOperand(0).getReg();
- }
- break;
- }
- return 0;
-}
-
-unsigned Thumb1InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
- int &FrameIndex) const {
- switch (MI->getOpcode()) {
- default: break;
- case ARM::tSpill:
- if (MI->getOperand(1).isFI() &&
- MI->getOperand(2).isImm() &&
- MI->getOperand(2).getImm() == 0) {
- FrameIndex = MI->getOperand(1).getIndex();
- return MI->getOperand(0).getReg();
- }
- break;
- }
- return 0;
-}
-
bool Thumb1InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned DestReg, unsigned SrcReg,
Modified: llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.h?rev=77174&r1=77173&r2=77174&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.h (original)
+++ llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.h Sun Jul 26 19:24:36 2009
@@ -50,11 +50,6 @@
MachineBasicBlock::iterator MI,
const std::vector<CalleeSavedInfo> &CSI) const;
- unsigned isLoadFromStackSlot(const MachineInstr *MI,
- int &FrameIndex) const;
- unsigned isStoreToStackSlot(const MachineInstr *MI,
- int &FrameIndex) const;
-
bool copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned DestReg, unsigned SrcReg,
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