[llvm-commits] [llvm] r76843 - in /llvm/trunk: lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/vec_insertps-1.ll

[Evan Cheng]

On Jul 23, 2009, at 11:50 AM, Eric Christopher wrote:

>
> On Jul 22, 2009, at 11:07 PM, Evan Cheng wrote:
>
>> Of course, the above change means the pattern for the memory form of
>> the instruction is also wrong:
>>
>>    def match_rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
>>                   (ins VR128:$src1, f32mem:$src2, i32i8imm:$src3),
>>                   !strconcat(OpcodeStr,
>>                    "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
>>                   [(set VR128:$dst,
>>                     (X86insrtps VR128:$src1, (loadf32 addr:$src2),
>>                                 imm:$src3))]>, OpSize;
>>
>> The pattern probably should be something like:
>> [(set VR128:$dst, (X86insrtps VR128:$src1, (v4f32 (scalar_to_vector
>> (loadf32 addr:$src2)), imm:$src3))]
>
> That's what's so annoying about this instruction it takes variable  
> sized arguments:
>
> insertps xmm0, xmm1/m32, imm8
>
> so I think the rm pattern is ok? With your change we'd be turning it  
> into an m128 yes? Or am I missing something? I'm not sure what side  
> effects this sort of thing has inside the instruction selection  
> machinery.

No, the rm instruction will not be selected. The input pattern is  
loading from f32 but it will then do a SCALAR_TO_VECTOR to v4f32. So  
you need to change the pattern to explicitly match that as well.

Evan


>
> -eric