[llvm-commits] LLVM Verilog Backend

[Nadav]

Hello,

My name is Nadav Rotem and I am a PhD student at Haifa University. In my
research (in High-level Synthesis), I developed a Verilog backend for LLVM
that I would like to contribute to LLVM. The Verilog Backend is documented
in an academic paper [1].  An on-line web interface is available [2].

I attached the code to this email. The code compiles with LLVM 2.5; I only
included the Backend itself. I did not include the preliminary
transformation passes, the driver scripts and the test cases.

Thank you,
Nadav Rotem | http://cs.haifa.ac.il/~rotemn/<http://cs.haifa.ac.il/%7Erotemn/>

[1] http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=4694874
[2] http://www.c-to-verilog.com
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