[llvm-commits] [llvm] r75919 - in /llvm/trunk: lib/Target/SystemZ/SystemZISelDAGToDAG.cpp lib/Target/SystemZ/SystemZInstrInfo.td test/CodeGen/SystemZ/02-RetAndImm.ll test/CodeGen/SystemZ/02-RetOrImm.ll
Anton Korobeynikov
asl at math.spbu.ru
Thu Jul 16 06:33:59 PDT 2009
Author: asl
Date: Thu Jul 16 08:33:57 2009
New Revision: 75919
URL: http://llvm.org/viewvc/llvm-project?rev=75919&view=rev
Log:
Provide masked reg-imm 'or' and 'and'
Modified:
llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
llvm/trunk/test/CodeGen/SystemZ/02-RetAndImm.ll
llvm/trunk/test/CodeGen/SystemZ/02-RetOrImm.ll
Modified: llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp?rev=75919&r1=75918&r2=75919&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp Thu Jul 16 08:33:57 2009
@@ -50,8 +50,14 @@
return "SystemZ DAG->DAG Pattern Instruction Selection";
}
+ /// getI16Imm - Return a target constant with the specified value, of type
+ /// i16.
+ inline SDValue getI16Imm(uint64_t Imm) {
+ return CurDAG->getTargetConstant(Imm, MVT::i16);
+ }
+
// Include the pieces autogenerated from the target description.
- #include "SystemZGenDAGISel.inc"
+ #include "SystemZGenDAGISel.inc"
private:
SDNode *Select(SDValue Op);
Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td?rev=75919&r1=75918&r2=75919&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td Thu Jul 16 08:33:57 2009
@@ -23,6 +23,50 @@
def NOP : Pseudo<(outs), (ins), "# no-op", []>;
//===----------------------------------------------------------------------===//
+// Instruction Pattern Stuff.
+//===----------------------------------------------------------------------===//
+def LL16 : SDNodeXForm<imm, [{
+ // Transformation function: return low 16 bits.
+ return getI16Imm(N->getZExtValue() & 0x000000000000FFFFULL);
+}]>;
+
+def LH16 : SDNodeXForm<imm, [{
+ // Transformation function: return bits 16-31.
+ return getI16Imm((N->getZExtValue() & 0x00000000FFFF0000ULL) >> 16);
+}]>;
+
+def HL16 : SDNodeXForm<imm, [{
+ // Transformation function: return bits 32-47.
+ return getI16Imm((N->getZExtValue() & 0x0000FFFF00000000ULL) >> 32);
+}]>;
+
+def HH16 : SDNodeXForm<imm, [{
+ // Transformation function: return bits 48-63.
+ return getI16Imm((N->getZExtValue() & 0xFFFF000000000000ULL) >> 48);
+}]>;
+
+def i64ll16 : PatLeaf<(i64 imm), [{
+ // i64ll16 predicate - true if the 64-bit immediate has only rightmost 16
+ // bits set.
+ return ((N->getZExtValue() & 0x000000000000FFFFULL) == N->getZExtValue());
+}], LL16>;
+
+def i64lh16 : PatLeaf<(i64 imm), [{
+ // i64lh16 predicate - true if the 64-bit immediate has only bits 16-31 set.
+ return ((N->getZExtValue() & 0x00000000FFFF0000ULL) == N->getZExtValue());
+}], LH16>;
+
+def i64hl16 : PatLeaf<(i64 imm), [{
+ // i64hl16 predicate - true if the 64-bit immediate has only bits 32-47 set.
+ return ((N->getZExtValue() & 0x0000FFFF00000000ULL) == N->getZExtValue());
+}], HL16>;
+
+def i64hh16 : PatLeaf<(i64 imm), [{
+ // i64hh16 predicate - true if the 64-bit immediate has only bits 48-63 set.
+ return ((N->getZExtValue() & 0xFFFF000000000000ULL) == N->getZExtValue());
+}], HH16>;
+
+//===----------------------------------------------------------------------===//
// Control Flow Instructions...
//
@@ -75,7 +119,20 @@
"ngr\t{$dst, $src2}",
[(set GR64:$dst, (and GR64:$src1, GR64:$src2))]>;
}
-// FIXME: provide patterns for masked and-with-imm
+
+// FIXME: Provide proper encoding!
+def AND64rill16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
+ "nill\t{$dst, $src2}",
+ [(set GR64:$dst, (and GR64:$src1, i64ll16:$src2))]>;
+def AND64rilh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
+ "nilh\t{$dst, $src2}",
+ [(set GR64:$dst, (and GR64:$src1, i64lh16:$src2))]>;
+def AND64rihl16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
+ "nihl\t{$dst, $src2}",
+ [(set GR64:$dst, (and GR64:$src1, i64hl16:$src2))]>;
+def AND64rihh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
+ "nihh\t{$dst, $src2}",
+ [(set GR64:$dst, (and GR64:$src1, i64hh16:$src2))]>;
let isCommutable = 1 in { // X = OR Y, Z == X = OR Z, Y
// FIXME: Provide proper encoding!
@@ -83,7 +140,18 @@
"ogr\t{$dst, $src2}",
[(set GR64:$dst, (or GR64:$src1, GR64:$src2))]>;
}
-// FIXME: provide patterns for masked or-with-imm
+def OR64rill16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
+ "oill\t{$dst, $src2}",
+ [(set GR64:$dst, (or GR64:$src1, i64ll16:$src2))]>;
+def OR64rilh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
+ "oilh\t{$dst, $src2}",
+ [(set GR64:$dst, (or GR64:$src1, i64lh16:$src2))]>;
+def OR64rihl16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
+ "oihl\t{$dst, $src2}",
+ [(set GR64:$dst, (or GR64:$src1, i64hl16:$src2))]>;
+def OR64rihh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
+ "oihh\t{$dst, $src2}",
+ [(set GR64:$dst, (or GR64:$src1, i64hh16:$src2))]>;
// FIXME: Provide proper encoding!
def SUB64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
Modified: llvm/trunk/test/CodeGen/SystemZ/02-RetAndImm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/02-RetAndImm.ll?rev=75919&r1=75918&r2=75919&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/02-RetAndImm.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/02-RetAndImm.ll Thu Jul 16 08:33:57 2009
@@ -1,9 +1,28 @@
-; RUN: llvm-as < %s | llc -march=systemz
-define i64 @foo(i64 %a, i64 %b) {
+; RUN: llvm-as < %s | llc -march=systemz | grep nill | count 1
+; RUN: llvm-as < %s | llc -march=systemz | grep nilh | count 1
+; RUN: llvm-as < %s | llc -march=systemz | grep nihl | count 1
+; RUN: llvm-as < %s | llc -march=systemz | grep nihh | count 1
+
+define i64 @foo1(i64 %a, i64 %b) {
entry:
%c = and i64 %a, 1
ret i64 %c
}
-; FIXME: SystemZ has 4 and reg-imm instructions depending on imm,
-; we need to support them someday.
\ No newline at end of file
+define i64 @foo2(i64 %a, i64 %b) {
+entry:
+ %c = and i64 %a, 131072
+ ret i64 %c
+}
+
+define i64 @foo3(i64 %a, i64 %b) {
+entry:
+ %c = and i64 %a, 8589934592
+ ret i64 %c
+}
+
+define i64 @foo4(i64 %a, i64 %b) {
+entry:
+ %c = and i64 %a, 562949953421312
+ ret i64 %c
+}
Modified: llvm/trunk/test/CodeGen/SystemZ/02-RetOrImm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/02-RetOrImm.ll?rev=75919&r1=75918&r2=75919&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/02-RetOrImm.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/02-RetOrImm.ll Thu Jul 16 08:33:57 2009
@@ -1,9 +1,28 @@
-; RUN: llvm-as < %s | llc -march=systemz
-define i64 @foo(i64 %a, i64 %b) {
+; RUN: llvm-as < %s | llc -march=systemz | grep oill | count 1
+; RUN: llvm-as < %s | llc -march=systemz | grep oilh | count 1
+; RUN: llvm-as < %s | llc -march=systemz | grep oihl | count 1
+; RUN: llvm-as < %s | llc -march=systemz | grep oihh | count 1
+
+define i64 @foo1(i64 %a, i64 %b) {
entry:
%c = or i64 %a, 1
ret i64 %c
}
-; FIXME: SystemZ has 4 or reg-imm instructions depending on imm,
-; we need to support them someday.
\ No newline at end of file
+define i64 @foo2(i64 %a, i64 %b) {
+entry:
+ %c = or i64 %a, 131072
+ ret i64 %c
+}
+
+define i64 @foo3(i64 %a, i64 %b) {
+entry:
+ %c = or i64 %a, 8589934592
+ ret i64 %c
+}
+
+define i64 @foo4(i64 %a, i64 %b) {
+entry:
+ %c = or i64 %a, 562949953421312
+ ret i64 %c
+}
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