[llvm-commits] [llvm] r75912 - in /llvm/trunk: lib/Target/SystemZ/AsmPrinter/SystemZAsmPrinter.cpp lib/Target/SystemZ/SystemZInstrInfo.cpp lib/Target/SystemZ/SystemZInstrInfo.td test/CodeGen/SystemZ/01-RetArg.ll test/CodeGen/SystemZ/01-RetImm.ll

[Anton Korobeynikov]

Author: asl
Date: Thu Jul 16 08:29:38 2009
New Revision: 75912

URL: http://llvm.org/viewvc/llvm-project?rev=75912&view=rev
Log:
Add simple reg-reg and reg-imm moves

Added:
    llvm/trunk/test/CodeGen/SystemZ/01-RetArg.ll
    llvm/trunk/test/CodeGen/SystemZ/01-RetImm.ll
Modified:
    llvm/trunk/lib/Target/SystemZ/AsmPrinter/SystemZAsmPrinter.cpp
    llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp
    llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td

Modified: llvm/trunk/lib/Target/SystemZ/AsmPrinter/SystemZAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/AsmPrinter/SystemZAsmPrinter.cpp?rev=75912&r1=75911&r2=75912&view=diff

==============================================================================
--- llvm/trunk/lib/Target/SystemZ/AsmPrinter/SystemZAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/AsmPrinter/SystemZAsmPrinter.cpp Thu Jul 16 08:29:38 2009
@@ -168,5 +168,20 @@
 
 void SystemZAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
                                     const char* Modifier) {
-  assert(0 && "Not implemented yet!");
+  const MachineOperand &MO = MI->getOperand(OpNum);
+  switch (MO.getType()) {
+  case MachineOperand::MO_Register:
+    assert (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
+            "Virtual registers should be already mapped!");
+    O << '%' << TM.getRegisterInfo()->get(MO.getReg()).AsmName;
+    return;
+  case MachineOperand::MO_Immediate:
+    O << MO.getImm();
+    return;
+  case MachineOperand::MO_MachineBasicBlock:
+    printBasicBlockLabel(MO.getMBB());
+    return;
+  default:
+    assert(0 && "Not implemented yet!");
+  }
 }

Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp?rev=75912&r1=75911&r2=75912&view=diff

==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp Thu Jul 16 08:29:38 2009
@@ -43,18 +43,46 @@
 }
 
 bool SystemZInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
-                                   MachineBasicBlock::iterator I,
-                                   unsigned DestReg, unsigned SrcReg,
-                                   const TargetRegisterClass *DestRC,
-                                   const TargetRegisterClass *SrcRC) const {
+                                    MachineBasicBlock::iterator I,
+                                    unsigned DestReg, unsigned SrcReg,
+                                    const TargetRegisterClass *DestRC,
+                                    const TargetRegisterClass *SrcRC) const {
+  DebugLoc DL = DebugLoc::getUnknownLoc();
+  if (I != MBB.end()) DL = I->getDebugLoc();
+
+  if (DestRC == SrcRC) {
+    unsigned Opc;
+    if (DestRC == &SystemZ::GR64RegClass) {
+      Opc = SystemZ::MOV64rr;
+    } else {
+      return false;
+    }
+
+    BuildMI(MBB, I, DL, get(Opc), DestReg).addReg(SrcReg);
+    return true;
+  }
+
   return false;
 }
 
 bool
 SystemZInstrInfo::isMoveInstr(const MachineInstr& MI,
-                             unsigned &SrcReg, unsigned &DstReg,
-                             unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
-  return false;
+                              unsigned &SrcReg, unsigned &DstReg,
+                              unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
+  SrcSubIdx = DstSubIdx = 0; // No sub-registers yet.
+
+  switch (MI.getOpcode()) {
+  default:
+    return false;
+  case SystemZ::MOV64rr:
+    assert(MI.getNumOperands() >= 2 &&
+           MI.getOperand(0).isReg() &&
+           MI.getOperand(1).isReg() &&
+           "invalid register-register move instruction");
+    SrcReg = MI.getOperand(1).getReg();
+    DstReg = MI.getOperand(0).getReg();
+    return true;
+  }
 }
 
 bool

Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td?rev=75912&r1=75911&r2=75912&view=diff

==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td Thu Jul 16 08:29:38 2009
@@ -30,3 +30,20 @@
 let isReturn = 1, isTerminator = 1 in {
   def RET : Pseudo<(outs), (ins), "br\t%r14", [(SystemZretflag)]>;
 }
+
+//===----------------------------------------------------------------------===//
+// Move Instructions
+
+// FIXME: Provide proper encoding!
+let neverHasSideEffects = 1 in {
+def MOV64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src),
+                     "lgr\t{$dst, $src}",
+                     []>;
+}
+
+// FIXME: Provide proper encoding!
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
+def MOV64ri : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
+                     "lghi\t{$dst, $src}",
+                     [(set GR64:$dst, imm:$src)]>;
+}

Added: llvm/trunk/test/CodeGen/SystemZ/01-RetArg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/01-RetArg.ll?rev=75912&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/01-RetArg.ll (added)
+++ llvm/trunk/test/CodeGen/SystemZ/01-RetArg.ll Thu Jul 16 08:29:38 2009
@@ -0,0 +1,6 @@
+; RUN: llvm-as < %s | llc -march=systemz
+
+define i64 @foo(i64 %a, i64 %b) {
+entry:
+    ret i64 %b
+}
\ No newline at end of file

Added: llvm/trunk/test/CodeGen/SystemZ/01-RetImm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/01-RetImm.ll?rev=75912&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/01-RetImm.ll (added)
+++ llvm/trunk/test/CodeGen/SystemZ/01-RetImm.ll Thu Jul 16 08:29:38 2009
@@ -0,0 +1,6 @@
+; RUN: llvm-as < %s | llc -march=systemz
+
+define i64 @foo() {
+entry:
+    ret i64 0
+}
\ No newline at end of file