[llvm-commits] [PATCH] MSIL backend: Int bit width printing modification

[Artur Pietrek]

On Tue, Jul 14, 2009 at 11:50 AM, Anton Korobeynikov <
anton at korobeynikov.info> wrote:

> Hi, Artur
>
> > This patch modifies ints' bit width to those supportet by MSIL.
> What will be with corresponding operations? Say, I have i7 add, will it
> be 'promoted' to i8?
>
> How you're dealing with the case when the result of operation wraps?


Hi Anton,
Thanks for pointing it out. I will "rethink" this problem and submit again
when have solution.

Artur
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