[llvm-commits] [PATCH] MSIL backend: Int bit width printing modification

[Anton Korobeynikov]

Hi, Artur

> This patch modifies ints' bit width to those supportet by MSIL.
What will be with corresponding operations? Say, I have i7 add, will it
be 'promoted' to i8? 

How you're dealing with the case when the result of operation wraps?

-- 
With best regards, Anton Korobeynikov.

Faculty of Mathematics & Mechanics, Saint Petersburg State University.