[llvm-commits] [llvm] r70724 - in /llvm/trunk/lib/Target/MSP430: MSP430ISelLowering.cpp MSP430InstrInfo.td MSP430RegisterInfo.td

[Anton Korobeynikov]

Author: asl
Date: Sun May  3 08:06:26 2009
New Revision: 70724

URL: http://llvm.org/viewvc/llvm-project?rev=70724&view=rev
Log:
Add normal and trunc stores

Modified:
    llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp
    llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.td
    llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.td

Modified: llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp?rev=70724&r1=70723&r2=70724&view=diff

==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp Sun May  3 08:06:26 2009
@@ -39,6 +39,7 @@
   TargetLowering(tm), Subtarget(*tm.getSubtargetImpl()), TM(tm) {
 
   // Set up the register classes.
+  addRegisterClass(MVT::i8,  MSP430::GR8RegisterClass);
   addRegisterClass(MVT::i16, MSP430::GR16RegisterClass);
 
   // Compute derived properties from the register classes
@@ -59,6 +60,9 @@
   setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
   setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
 
+  // We don't have any truncstores
+  setTruncStoreAction(MVT::i16, MVT::i8, Expand);
+
   setOperationAction(ISD::SRA, MVT::i16, Custom);
   setOperationAction(ISD::RET, MVT::Other, Custom);
 }

Modified: llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.td?rev=70724&r1=70723&r2=70724&view=diff

==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.td (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.td Sun May  3 08:06:26 2009
@@ -35,12 +35,17 @@
 // MSP430 Operand Definitions.
 //===----------------------------------------------------------------------===//
 
-// Address operand
+// Address operands
 def memsrc : Operand<i16> {
   let PrintMethod = "printSrcMemOperand";
   let MIOperandInfo = (ops i16imm, GR16);
 }
 
+def memdst : Operand<i16> {
+  let PrintMethod = "printSrcMemOperand";
+  let MIOperandInfo = (ops i16imm, GR16);
+}
+
 
 //===----------------------------------------------------------------------===//
 // MSP430 Complex Pattern Definitions.
@@ -106,6 +111,20 @@
                 "mov.b\t{$src, $dst|$dst, $src}",
                 [(set GR16:$dst, (zextloadi16i8 addr:$src))]>;
 
+def MOV8mi  : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
+                "mov.b\t{$src, $dst|$dst, $src}",
+                [(store (i8 imm:$src), addr:$dst)]>;
+def MOV16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
+                "mov.w\t{$src, $dst|$dst, $src}",
+                [(store (i16 imm:$src), addr:$dst)]>;
+
+def MOV8mr  : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
+                "mov.b\t{$src, $dst|$dst, $src}",
+                [(store GR8:$src, addr:$dst)]>;
+def MOV16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
+                "mov.w\t{$src, $dst|$dst, $src}",
+                [(store GR16:$src, addr:$dst)]>;
+
 //===----------------------------------------------------------------------===//
 // Arithmetic Instructions
 
@@ -273,3 +292,7 @@
 
 // extload
 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
+
+// truncs
+def : Pat<(i8 (trunc GR16:$src)),
+          (EXTRACT_SUBREG GR16:$src, subreg_8bit)>;

Modified: llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.td?rev=70724&r1=70723&r2=70724&view=diff

==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.td (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.td Sun May  3 08:06:26 2009
@@ -65,6 +65,8 @@
                    [PCB, SPB, SRB, CGB, FPB,
                     R5B, R6B, R7B, R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
 
+def subreg_8bit : PatLeaf<(i32 1)>;
+
 def GR8 : RegisterClass<"MSP430", [i8], 8,
    // Volatile registers
   [R12B, R13B, R14B, R15B, R11B, R10B, R9B, R8B, R7B, R6B, R5B,