[llvm-commits] [llvm] r70723 - in /llvm/trunk/lib/Target/MSP430: MSP430AsmPrinter.cpp MSP430ISelDAGToDAG.cpp MSP430ISelLowering.cpp MSP430InstrInfo.td
Anton Korobeynikov
asl at math.spbu.ru
Sun May 3 06:06:04 PDT 2009
Author: asl
Date: Sun May 3 08:06:03 2009
New Revision: 70723
URL: http://llvm.org/viewvc/llvm-project?rev=70723&view=rev
Log:
Basic support for mem=>reg moves
Modified:
llvm/trunk/lib/Target/MSP430/MSP430AsmPrinter.cpp
llvm/trunk/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp
llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.td
Modified: llvm/trunk/lib/Target/MSP430/MSP430AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430AsmPrinter.cpp?rev=70723&r1=70722&r2=70723&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430AsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430AsmPrinter.cpp Sun May 3 08:06:03 2009
@@ -47,7 +47,10 @@
return "MSP430 Assembly Printer";
}
- void printOperand(const MachineInstr *MI, int OpNum);
+ void printOperand(const MachineInstr *MI, int OpNum,
+ const char* Modifier = 0);
+ void printSrcMemOperand(const MachineInstr *MI, int OpNum,
+ const char* Modifier = 0);
bool printInstruction(const MachineInstr *MI); // autogenerated.
void printMachineInstruction(const MachineInstr * MI);
bool runOnMachineFunction(MachineFunction &F);
@@ -119,7 +122,8 @@
assert(0 && "Should not happen");
}
-void MSP430AsmPrinter::printOperand(const MachineInstr *MI, int OpNum) {
+void MSP430AsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
+ const char* Modifier) {
const MachineOperand &MO = MI->getOperand(OpNum);
switch (MO.getType()) {
case MachineOperand::MO_Register:
@@ -129,7 +133,9 @@
assert(0 && "not implemented");
break;
case MachineOperand::MO_Immediate:
- O << "#" << MO.getImm();
+ if (!Modifier || strcmp(Modifier, "nohash"))
+ O << '#';
+ O << MO.getImm();
break;
case MachineOperand::MO_MachineBasicBlock:
printBasicBlockLabel(MO.getMBB());
@@ -138,3 +144,21 @@
assert(0 && "Not implemented yet!");
}
}
+
+void MSP430AsmPrinter::printSrcMemOperand(const MachineInstr *MI, int OpNum,
+ const char* Modifier) {
+ const MachineOperand &Disp = MI->getOperand(OpNum);
+ assert(Disp.isImm() && "Displacement can be only immediate!");
+
+ // Special case: 0(Reg) -> @Reg
+ if (Disp.getImm() == 0) {
+ O << "@";
+ printOperand(MI, OpNum + 1);
+ } else {
+ printOperand(MI, OpNum, "nohash");
+ O << '(';
+ printOperand(MI, OpNum + 1);
+ O << ')';
+ }
+}
+
Modified: llvm/trunk/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp?rev=70723&r1=70722&r2=70723&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp Sun May 3 08:06:03 2009
@@ -57,6 +57,7 @@
private:
SDNode *Select(SDValue Op);
+ bool SelectAddr(SDValue Op, SDValue Addr, SDValue &Disp, SDValue &Base);
#ifndef NDEBUG
unsigned Indent;
@@ -71,6 +72,38 @@
return new MSP430DAGToDAGISel(TM);
}
+bool MSP430DAGToDAGISel::SelectAddr(SDValue Op, SDValue Addr,
+ SDValue &Disp, SDValue &Base) {
+ // We don't support frame index stuff yet.
+ if (isa<FrameIndexSDNode>(Addr))
+ return false;
+
+ // Operand is a result from ADD with constant operand which fits into i16.
+ if (Addr.getOpcode() == ISD::ADD) {
+ if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
+ uint64_t CVal = CN->getZExtValue();
+ // Offset should fit into 16 bits.
+ if (((CVal << 48) >> 48) == CVal) {
+ // We don't support frame index stuff yet.
+ if (isa<FrameIndexSDNode>(Addr.getOperand(0)))
+ return false;
+
+ Base = Addr.getOperand(0);
+ Disp = CurDAG->getTargetConstant(CVal, MVT::i16);
+
+ return true;
+ }
+ }
+ }
+
+ Base = Addr;
+ Disp = CurDAG->getTargetConstant(0, MVT::i16);
+
+ return true;
+}
+
+
+
/// InstructionSelect - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
void MSP430DAGToDAGISel::InstructionSelect() {
Modified: llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp?rev=70723&r1=70722&r2=70723&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp Sun May 3 08:06:03 2009
@@ -53,6 +53,12 @@
// shifts of the whole bitwidth 1 bit per step.
setShiftAmountType(MVT::i8);
+ setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
+ setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
+ setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
+ setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
+ setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
+
setOperationAction(ISD::SRA, MVT::i16, Custom);
setOperationAction(ISD::RET, MVT::Other, Custom);
}
Modified: llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.td?rev=70723&r1=70722&r2=70723&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.td (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.td Sun May 3 08:06:03 2009
@@ -32,15 +32,35 @@
def MSP430rra : SDNode<"MSP430ISD::RRA", SDTIntUnaryOp, []>;
//===----------------------------------------------------------------------===//
-// Pseudo Instructions
+// MSP430 Operand Definitions.
+//===----------------------------------------------------------------------===//
+
+// Address operand
+def memsrc : Operand<i16> {
+ let PrintMethod = "printSrcMemOperand";
+ let MIOperandInfo = (ops i16imm, GR16);
+}
+
+
+//===----------------------------------------------------------------------===//
+// MSP430 Complex Pattern Definitions.
+//===----------------------------------------------------------------------===//
+
+def addr : ComplexPattern<iPTR, 2, "SelectAddr", [], []>;
+
+//===----------------------------------------------------------------------===//
+// Pattern Fragments
+def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
+def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 ( extloadi8 node:$ptr))>;
+
//===----------------------------------------------------------------------===//
+// Pseudo Instructions
let neverHasSideEffects = 1 in
def NOP : Pseudo<(outs), (ins), "nop", []>;
//===----------------------------------------------------------------------===//
// Real Instructions
-//===----------------------------------------------------------------------===//
// FIXME: Provide proper encoding!
let isReturn = 1, isTerminator = 1 in {
@@ -52,25 +72,40 @@
// FIXME: Provide proper encoding!
let neverHasSideEffects = 1 in {
-def MOV16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src),
- "mov.w\t{$src, $dst|$dst, $src}",
- []>;
def MOV8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src),
"mov.b\t{$src, $dst|$dst, $src}",
[]>;
+def MOV16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src),
+ "mov.w\t{$src, $dst|$dst, $src}",
+ []>;
}
// FIXME: Provide proper encoding!
let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
-def MOV16ri : Pseudo<(outs GR16:$dst), (ins i16imm:$src),
- "mov.w\t{$src, $dst|$dst, $src}",
- [(set GR16:$dst, imm:$src)]>;
def MOV8ri : Pseudo<(outs GR8:$dst), (ins i8imm:$src),
"mov.b\t{$src, $dst|$dst, $src}",
[(set GR8:$dst, imm:$src)]>;
+def MOV16ri : Pseudo<(outs GR16:$dst), (ins i16imm:$src),
+ "mov.w\t{$src, $dst|$dst, $src}",
+ [(set GR16:$dst, imm:$src)]>;
+}
+let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
+def MOV8rm : Pseudo<(outs GR8:$dst), (ins memsrc:$src),
+ "mov.b\t{$src, $dst|$dst, $src}",
+ [(set GR8:$dst, (load addr:$src))]>;
+def MOV16rm : Pseudo<(outs GR16:$dst), (ins memsrc:$src),
+ "mov.w\t{$src, $dst|$dst, $src}",
+ [(set GR16:$dst, (load addr:$src))]>;
}
+def MOVZX16rr8 : Pseudo<(outs GR16:$dst), (ins GR8:$src),
+ "mov.b\t{$src, $dst|$dst, $src}",
+ [(set GR16:$dst, (zext GR8:$src))]>;
+def MOVZX16rm8 : Pseudo<(outs GR16:$dst), (ins memsrc:$src),
+ "mov.b\t{$src, $dst|$dst, $src}",
+ [(set GR16:$dst, (zextloadi16i8 addr:$src))]>;
+
//===----------------------------------------------------------------------===//
// Arithmetic Instructions
@@ -232,3 +267,9 @@
[(set GR8:$dst, (or GR8:$src1, imm:$src2))]>;
} // isTwoAddress = 1
+
+//===----------------------------------------------------------------------===//
+// Non-Instruction Patterns
+
+// extload
+def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
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